James E. Smith

Affiliations:
  • University of Wisconsin-Madison, WI, USA


According to our database1, James E. Smith authored at least 118 papers between 1978 and 2021.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Superconducting Computing with Alternating Logic Elements.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing.
CoRR, 2020

2018
Space-Time Algebra: A Model for Neocortical Computation.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Space-Time Computing with Temporal Neural Networks
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01754-4, 2017

Research Agenda: Spacetime Computation and the Neocortex.
IEEE Micro, 2017

2014
Efficient digital neurons for large scale cortical architectures.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
The role of computer designers in reverse-engineering the brain.
Proceedings of the International Conference on Supercomputing, 2013

2009
A mechanistic performance model for superscalar out-of-order processors.
ACM Trans. Comput. Syst., 2009

2008
Multicore Resource Management.
IEEE Micro, 2008

Implementing high availability memory with a duplication cache.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Power-Efficient DRAM Speculation.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
A Top-Down Approach to Architecting CPI Component Performance Counters.
IEEE Micro, 2007

Isolation in Commodity Multicore Processors.
Computer, 2007

Virtual private caches.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Automated design of application specific superscalar processors: an analytical approach.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Configurable isolation: building high availability systems with commodity multi-core processors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Implicit Transactional Memory in Kilo-Instruction Multiprocessors.
Proceedings of the Advances in Computer Systems Architecture, 2007

Studying Compiler-Microarchitecture Interactions through Interval Analysis.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays.
IEEE Micro, 2006

Tuning adaptive microarchitectures.
Int. J. Embed. Syst., 2006

The Future of Simulation: A Field of Dreams.
Computer, 2006

Fair Queuing Memory Systems.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Characterizing the branch misprediction penalty.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Reducing Startup Time in Co-Designed Virtual Machines.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

An approach for implementing efficient superscalar CISC processors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

A performance counter architecture for computing accurate CPI components.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Stealth prefetching.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
The Complexity of Verifying Memory Coherence and Consistency.
IEEE Trans. Parallel Distributed Syst., 2005

Data Cache Prefetching Using a Global History Buffer.
IEEE Micro, 2005

A unified view of virtualization.
Proceedings of the 1st International Conference on Virtual Execution Environments, 2005

Runtime specialization with optimistic heap analysis.
Proceedings of the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2005

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Implementing Kilo-Instruction Multiprocessors.
Proceedings of the International Conference on Pervasive Services 2005, 2005

Value Compression for Efficient Computation.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2004
The future of simulation: A field of dreams.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

A First-Order Superscalar Processor Model.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Tuning Reconfigurable Microarchitectures for Power Efficiency.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Using Dynamic Binary Translation to Fuse Dependent Instructions.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Software-Controlled Operand-Gating.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Some Real Observations on Virtual Machines.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

AC/DC: An Adaptive Data Cache Prefetcher.
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003
Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox.
IEEE Micro, 2003

The complexity of verifying memory coherence.
Proceedings of the SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2003

Hardware Support for Control Transfers in Code Caches.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Comparing Program Phase Detection Techniques.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Keynote: Is there anything more to learn about high performance processors?
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Dynamic Binary Translation for Accumulator-Oriented Architectures.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002
Integrated Performance, Power, and Thermal Modeling.
J. Circuits Syst. Comput., 2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Saving energy with just in time instruction delivery.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

An Instruction Set and Microarchitecture for Instruction Level Distributed Processing.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Managing Multi-Configuration Hardware via Dynamic Working Set Analysis.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Dual path instruction processing.
Proceedings of the 16th international conference on Supercomputing, 2002

Statistical Simulation of Symmetric Multiprocessor Systems.
Proceedings of the Proceedings 35th Annual Simulation Symposium (ANSS-35 2002), 2002

2001
Instruction-Level Distributed Processing.
Computer, 2001

Rapid profiling via stratified sampling.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Modeling Superscalar Processors via Statistical Simulation.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
Control Independence in Trace Processors.
J. Instr. Level Parallelism, 2000

Relational profiling: enabling thread-level parallelism in virtual machines.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Very low power pipelines using significance compression.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Concurrent Garbage Collection UsingHardware-Assisted Profiling.
Proceedings of the ISMM 2000, 2000

Instruction Level Distributed Processing: Adapting to Future Technology.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Vector instruction set support for conditional operations.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Trace preconstruction.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1999
A Trace Cache Microarchitecture and Evaluation.
IEEE Trans. Computers, 1999

Limits of Data Value Predictability.
Int. J. Parallel Program., 1999

Improving Branch Predictors by Correlating on Data Values.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

A Study of Control Independence in Superscalar Processors.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Instruction Pre-Processing in Trace Processors.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Exploiting Idle Floating-Point Resources for Integer Execution.
Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998

Implementation of Precise Interupts in Pipelined Processors.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Implementing Precise Interrupts in Pipelined Processors.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Decoupled Access/Execute Architectures.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: A Study of Branch Prediction Strategies.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Modeling Program Predictability.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Vector Architectures: Past, Present and Future.
Proceedings of the 12th international conference on Supercomputing, 1998

Speculative Versioning Cache.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1997
The Predictability of Data Values.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Trace Processors.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Path-Based Next Trace Prediction.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Out-of-Order Vector Architectures.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Complexity-Effective Superscalar Processors.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Control Flow Speculation in Multiscalar Processors.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
The Performance Potential of Data Dependence Speculation & Collapsing.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Assigning Confidence to Conditional Branch Predictions.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995
Decoupling integer execution in superscalar processors.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994
PowerPC 601 and Alpha 21064: A Tale of Two RISCs.
Computer, 1994

Cache performance in vector supercomputers.
Proceedings of the Proceedings Supercomputing '94, 1994

1992
A Study of Partitioned Vector Register Files.
Proceedings of the Proceedings Supercomputing '92, 1992

1990
A study of scalar compilation techniques for pipelined supercomputers.
ACM Trans. Math. Softw., 1990

1989
Dynamic Instruction Scheduling and the Astronautics ZS-1.
Computer, 1989

Restricted Fetch&Phi operations for parallel processing.
Proceedings of the 3rd international conference on Supercomputing, 1989

An accurate, high speed implementation of division by reciprocal approximation.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988
Characterizing Computer Performance with a Single Number.
Commun. ACM, 1988

The Astronautics ZS-1 processor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987
The ZS-1 Central Processor.
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987

1986
A Simulation Study of Decoupled Architecture Computers.
IEEE Trans. Computers, 1986

Optimal Pipelining in Supercomputers.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Pipelined Register-Storage Architectures.
Proceedings of the International Conference on Parallel Processing, 1986

1985
Self-Diagnosis in Distributed Systems.
IEEE Trans. Computers, 1985

Implementation of Precise Interrupts in Pipelined Processors.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984
Decoupled Access/Execute Computer Architectures
ACM Trans. Comput. Syst., 1984

Instruction Issue Logic in Pipelined Supercomputers.
IEEE Trans. Computers, 1984

On Separable Unordered Codes.
IEEE Trans. Computers, 1984

1983
A Theory of Totally Self-Checking System Design.
IEEE Trans. Computers, 1983

1982
Developments in logic network path delay analysis.
Proceedings of the 19th Design Automation Conference, 1982

1981
Diagnosis of Systems with Asymmetric Invalidation.
IEEE Trans. Computers, 1981

A Study of Branch Prediction Strategies.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

1980
Measures of the Effectiveness of Fault Signature Analysis.
IEEE Trans. Computers, 1980

1979
Comments on "Redundancy Testing in Combinational Networks".
IEEE Trans. Computers, 1979

Detection of Faults in Programmable Logic Arrays.
IEEE Trans. Computers, 1979

On Necessary and Sufficient Conditions for Multiple Fault Undetectability.
IEEE Trans. Computers, 1979

Universal System Diagnosis Algorithms.
IEEE Trans. Computers, 1979

1978
Strongly Fault Secure Logic Networks.
IEEE Trans. Computers, 1978

On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy.
IEEE Trans. Computers, 1978


  Loading...