Symmetric Bipartite Tables for Accurate Function Approximation. - Michael J. Schulte; James E. Stine (IEEE Symposium on Computer Arithmetic, 1997)

Accurate Function Approximations by Symmetric Table Lookup and Addition. - Michael J. Schulte; James E. Stine (ASAP, 1997)

A Combined Interval and Floating Point Multiplier. - James E. Stine; Michael J. Schulte (Great Lakes Symposium on VLSI, 1998)

Approximating Elementary Functions with Symmetric Bipartite Tables. - Michael J. Schulte; James E. Stine (IEEE Trans. Computers, 1999)

The Symmetric Table Addition Method for Accurate Function Approximation. - James E. Stine; Michael J. Schulte (J. VLSI Signal Process., 1999)

Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. - Kent E. Wires; Michael J. Schulte; James E. Stine (ICCD, 2001)

Variations on Truncated Multiplication. - James E. Stine; Oliver M. Duverne (DSD, 2003)

A pipelined clock-delayed domino carry-lookahead adder. - Bhushan A. Shinkre; James E. Stine (ACM Great Lakes Symposium on VLSI, 2003)

A Standard Cell Library for Student Projects. - Johannes Grad; James E. Stine (MSE, 2003)

Modified booth truncated multipliers. - Alok A. Katkar; James E. Stine (ACM Great Lakes Symposium on VLSI, 2004)

Parallel Programmable Finite Field GF(2m) Multipliers. - Nick Iliev; James E. Stine; Nathan Jachimiec (ISVLSI, 2004)

Intrinsic Compiler Support for Interval Arithmetic. - Ahmet Akkas; Michael J. Schulte; James E. Stine (Numer. Algorithms, 2004)

New algorithms for carry propagation. - Johannes Grad; James E. Stine (ACM Great Lakes Symposium on VLSI, 2005)

Constant addition utilizing flagged prefix structures. - James E. Stine; Christopher R. Babb; Vibhuti B. Dave (ISCAS (1), 2005)

A combined two's complement and floating-point comparator. - James E. Stine; Michael J. Schulte (ISCAS (1), 2005)

Real World SOC Experience for the Classroom. - Johannes Grad; James E. Stine; David D. Neiman (MSE, 2005)

A Framework for High-Level Synthesis of System-on-Chip Designs. - James E. Stine; Johannes Grad; Ivan D. Castellanos; Jeff M. Blank; Vibhuti B. Dave; Mallika Prakash; Nick Iliev; Nathan Jachimiec (MSE, 2005)

A 64-bit Decimal Floating-Point Comparator. - Ivan D. Castellanos; James E. Stine (ASAP, 2006)

Low power binary addition using carry increment adders. - Johannes Grad; James E. Stine (ISCAS, 2006)

Compressed symmetric tables for accurate function approximation of reciprocals. - James E. Stine; Nitin Naresh (ISCAS, 2006)

Dual-Mode High-Speed Low-Energy Binary Addition. - Johannes Grad; James E. Stine (ISVLSI, 2006)

Partial Product Reduction for Parallel Cubing. - James E. Stine; Jeff M. Blank (ISVLSI, 2007)

FreePDK: An Open-Source Variation-Aware Design Kit. - James E. Stine; Ivan D. Castellanos; Michael H. Wood; Jeff Henson; Fred Love; W. Rhett Davis; Paul D. Franzon; Michael Bucher; Sunil Basavarajaiah; Julie Oh; Ravi Jenkal (MSE, 2007)

Single-ended half-swing low-power SRAM design. - Harsha Choday; James E. Stine (ACSCC, 2008)

Session WA5b: Low power methods. - James E. Stine (ACSCC, 2008)

Compressor trees for decimal partial product reduction. - Ivan D. Castellanos; James E. Stine (ACM Great Lakes Symposium on VLSI, 2008)

Parallel Prefix Ling Structures for Modulo 2^n-1 Addition. - Jun Chen; James E. Stine (ASAP, 2009)

FreePDK v2.0: Transitioning VLSI education towards nanometer variation-aware designs. - James E. Stine; Jun Chen; Ivan D. Castellanos; Gopal Sundararajan; Mohammad A. Qayum; Praveen Kumar; Justin Remington; Sohum Sohoni (MSE, 2009)

A recursive-divide architecture for multiplication and division. - James E. Stine; Amey Phadke; Surpriya Tike (ISCAS, 2011)

Optimized low-power elementary function approximation for Chebyshev series approximations. - Masoud Sadeghian; James E. Stine (ACSCC, 2012)

Session TA6b: Low power II (invited). - James E. Stine (ACSCC, 2012)

Elementary function approximation using optimized most significant bits of Chebyshev coefficients and truncated multipliers. - Masoud Sadeghian; James E. Stine (MWSCAS, 2012)

Additional optimizations for parallel squarer units. - Son Bui; James E. Stine (ISCAS, 2014)

Optimized cubic chebyshev interpolator for elementary function hardware implementations. - Masoud Sadeghian; James E. Stine; E. George Walters III (ISCAS, 2014)

Enhancing the Unified Logical Effort algorithm for branching and load distribution. - Mehedi Sarwar; James E. Stine (ISCAS, 2014)

Experiments with High Speed Parallel Cubing Units. - Son Bui; James E. Stine; Masoud Sadeghian (ISVLSI, 2014)

An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers. - S. Ross Thompson; James E. Stine (ASAP, 2015)

Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. - Samira Ataei; James E. Stine (ACM Great Lakes Symposium on VLSI, 2015)

A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. - Samira Ataei; James E. Stine (IGSC, 2015)

Revisiting redundant Booth with bias multipliers. - Sampoorna Mallipeddi; James E. Stine (MWSCAS, 2015)

Optimized multipartite table methods for elementary function computation. - James E. Stine; Masoud Sadeghian (ACSSC, 2016)

OpenRAM: an open-source memory compiler. - Matthew R. Guthaus; James E. Stine; Samira Ataei; Brian Chen; Bin Wu; Mehedi Sarwar (ICCAD, 2016)

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. - Samira Ataei; James E. Stine; Matthew R. Guthaus (ICCD, 2016)

A combined IEEE half and single precision floating point multipliers for deep learning. - Tuan D. Nguyen; James E. Stine (ACSSC, 2017)

A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. - Samira Ataei; James E. Stine (ACM Great Lakes Symposium on VLSI, 2017)

Sustainable IC design and fabrication. - Donald Kline Jr.; Nikolas Parshook; Alex Johnson; James E. Stine; William E. Stanchina; Erik Brunvand; Alex K. Jones (IGSC, 2017)

WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. - Rabin Thapa; Samira Ataei; James E. Stine (MSE, 2017)

A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. - Samira Ataei; Matthew Gaalswyk; James E. Stine (MWSCAS, 2017)

Constant-based truncated cubing architectures. - Son Bui; James E. Stine (MWSCAS, 2017)

Low-Area Memoryless optimized Soft-Decision Viterbi Decoder with Dedicated Paralell Squaring Architecture. - John D. Tobola; James E. Stine (ACSSC, 2018)

Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication. - Tuan D. Nguyen; Son Bui; James E. Stine (ASAP, 2018)

A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. - Samira Ataei; James E. Stine (SoCC, 2018)

A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. - Samira Ataei; James E. Stine (IEEE Embed. Syst. Lett., 2018)

Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. - Milos D. Ercegovac; James E. Stine (ACSSC, 2019)

A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. - Brett Mathis; James E. Stine (ASAP, 2019)

Fast and Area-Efficient SRAM Word-Line Optimization. - Bin Wu; James E. Stine; Matthew R. Guthaus (ISCAS, 2019)

A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition. - Matthew Gaalswyk; James E. Stine (ISVLSI, 2019)

A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. - Brett Mathis; James E. Stine (ISVLSI, 2019)

Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures. - Kyle Price; James E. Stine (MWSCAS, 2019)

An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education. - Alexander Underwood; James E. Stine (WCAE@ISCA, 2019)

An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. - James E. Stine; Milos D. Ercegovac; Jean-Michel Muller (ACSSC, 2020)

A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier. - S. Ross Thompson; James E. Stine (ICCD, 2020)

An Efficient Implementation of Radix-4 Integer Division Using Scaling. - James E. Stine; Kevin Hill (MWSCAS, 2020)

An Improved Hardware Architecture for modulo without Multiplication. - Ryan Swann; James E. Stine (MWSCAS, 2020)

A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication. - S. Ross Thompson; James E. Stine (MWSCAS, 2020)

A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware. - Ryan Swann; James E. Stine (ACSCC, 2021)

A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. - Teodor-Dumitru Ene; James E. Stine (ICCD, 2021)

Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees. - Teodor-Dumitru Ene; James E. Stine (ARITH, 2022)

Implementation of High Performance IEEE 754-Posit Conversion Hardware. - Brett Mathis; James E. Stine (ISCAS, 2022)

Parallelization of the Shift and Add Reducer. - Ryan Swann; James E. Stine (ACSSC, 2023)

Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures. - Alexander Underwood; James E. Stine (ACSSC, 2023)

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. - Matthew Guthaus; Christopher Batten; Erik Brunvand; Pierre-Emmanuel Gaillardon; David M. Harris; Rajit Manohar; Pinaki Mazumder; Larry T. Pileggi; James E. Stine (CoRR, 2023)

Evaluation of a Modular Approach to AES Hardware Architecture and Optimization. - Ryan Swann; James E. Stine (J. Signal Process. Syst., 2023)

Methodologies for Implementation of Standard-Cell Libraries for Radiation Hardened Environments. - Ryan Ridley; James E. Stine; George Suárez (LASCAS, 2024)

Power Reduction of Montgomery Multiplication Architectures Using Clock Gating. - Rachana Erra; James E. Stine (MWSCAS, 2024)

CharLib: An Open Source Standard Cell Library Characterizer. - Marcus Mellor; James E. Stine (MWSCAS, 2024)

Unified Digit Selection for Radix-4 Recurrence Division and Square Root. - David M. Harris; James E. Stine; Milos D. Ercegovac; Alberto Nannarelli; Katherine Parry; Cedar Turek (IEEE Trans. Computers, 2024)

Alchemy : A Methodology for Scalable RTL Design Space Exploration. - Ryan Swann; James E. Stine (ACM Great Lakes Symposium on VLSI, 2025)

Design of a Robust IEEE Compliant Floating - Point Divide and Square Root Using Iterative Approximation. - Carson Sager; James E. Stine (LASCAS, 2025)

Shared Recurrence Floating-Point Divide/Sqrt and Integer Divide/Remainder With Early Termination. - Kevin Kim; Katherine Parry; David M. Harris; Cedar Turek; Alessandro Maiuolo; Rose Thompson; James E. Stine (IEEE Trans. Computers, 2025)