Digital Integrated Circuit Testing using Transient Signal Analysis. - James F. Plusquellic; Donald M. Chiarulli; Steven P. Levitan (ITC, 1996)

Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data. - James F. Plusquellic; Donald M. Chiarulli; Steven P. Levitan (ITC, 1997)

Characterization of CMOS Defects using Transient Signal Analysis. - James F. Plusquellic; Donald M. Chiarulli; Steven P. Levitan (DFT, 1998)

8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects. - James F. Plusquellic; Amy Germida; Zheng Yan (DFT, 1999)

Defect detection using power supply transient signal analysis. - Amy Germida; Zheng Yan; James F. Plusquellic; Fidel Muradali (ITC, 1999)

Predicting device performance from pass/fail transient signal analysis data. - James F. Plusquellic; Amy Germida; Jonathan Hudson; Ernesto Staroswiecki; Chintan Patel (ITC, 2000)

Detection of CMOS Defects under Variable Processing Conditions. - Amy Germida; James F. Plusquellic (VTS, 2000)

Power supply transient signal integration circuit. - Chintan Patel; Fidel Muradali; James F. Plusquellic (ITC, 2001)

Detecting delay faults using power supply transient signal analysis. - Abhishek Singh 001; Chintan Patel; Shirong Liao; James F. Plusquellic; Anne E. Gattiker (ITC, 2001)

A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. - Chintan Patel; Jim Plusquellic (VTS, 2001)

IC Diagnosis Using Multiple Supply Pad IDDQs. - Jim Plusquellic (IEEE Des. Test Comput., 2001)

Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. - Abhishek Singh 001; Jim Plusquellic; Anne E. Gattiker (VTS, 2002)

Comparison of Branching CORDIC Implementations. - Abhishek Singh 001; Dhananjay S. Phatak; Tom Goff; Mike Riggs; James F. Plusquellic; Chintan Patel (ASAP, 2003)

FPGA implementation of a fast Hadamard transformer for WCDMA. - Sanat Kamal Bahl; Jim Plusquellic (FPGA, 2003)

Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. - Abhishek Singh 001; Jitin Tharian; Jim Plusquellic (ICCAD, 2003)

Impedance Profile of a Commercial Power Grid and Test System. - Dhruva Acharyya; Jim Plusquellic (ITC, 2003)

IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping. - Dhananjay S. Phatak; Tom Goff; Jim Plusquellic (Comput. Networks, 2003)

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. - Chintan Patel; Ernesto Staroswiecki; Smita Pawar; Dhruva Acharyya; Jim Plusquellic (J. Electron. Test., 2003)

Power supply transient signal analysis for defect-oriented test. - James F. Plusquellic; Abhishek Singh 001; Chintan Patel; Anne E. Gattiker (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. - Chintan Patel; Abhishek Singh 001; Jim Plusquellic (ITC, 2004)

On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. - Abhishek Singh 001; Chintan Patel; Jim Plusquellic (ITC, 2004)

Fault Simulation Model for i{DDT} Testing: An Investigation. - Abhishek Singh 001; Chintan Patel; Jim Plusquellic (VTS, 2004)

Securing Scan Design Using Lock and Key Technique. - Jeremy Lee; Mohammad Tehranipoor; Chintan Patel; Jim Plusquellic (DFT, 2005)

Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. - Dhruva Acharyya; Jim Plusquellic (VTS, 2005)

At-Speed Transition Fault Testing With Low Speed Scan Enable. - Nisar Ahmed; C. P. Ravikumar; Mohammad Tehranipoor; Jim Plusquellic (VTS, 2005)

Defect Detection Using Quiescent Signal Analysis. - Chintan Patel; Abhishek Singh 001; Jim Plusquellic (J. Electron. Test., 2005)

A Comparitive Study of W-cdma Cell Search Designs. - Sanat Kamal Bahl; James F. Plusquellic; Joseph Thomas (J. Circuits Syst. Comput., 2005)

A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. - Jeremy Lee; Mohammad Tehranipoor; Jim Plusquellic (VTS, 2006)

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. - Jim Plusquellic; Dhruva Acharyya; Abhishek Singh 001; Mohammad Tehranipoor; Chintan Patel (IEEE Des. Test Comput., 2006)

Defect Simulation Methodology for iDDT Testing. - Abhishek Singh 001; Jim Plusquellic; Dhananjay S. Phatak; Chintan Patel (J. Electron. Test., 2006)

Securing Designs against Scan-Based Side-Channel Attacks. - Jeremy Lee; Mohammad Tehranipoor; Chintan Patel; Jim Plusquellic (IEEE Trans. Dependable Secur. Comput., 2007)

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis. - Xiaoxiao Wang 001; Hassan Salmani; Mohammad Tehranipoor; James F. Plusquellic (DFT, 2008)

Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals. - Reza M. Rad; Jim Plusquellic; Mohammad Tehranipoor (HOST, 2008)

Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. - Xiaoxiao Wang 001; Mohammad Tehranipoor; Jim Plusquellic (HOST, 2008)

Power supply signal calibration techniques for improving detection resolution to hardware Trojans. - Reza M. Rad; Xiaoxiao Wang 001; Mohammad Tehranipoor; Jim Plusquellic (ICCAD, 2008)

A physical unclonable function defined using power distribution system equivalent resistance variations. - Ryan Helinski; Dhruva Acharyya; Jim Plusquellic (DAC, 2009)

New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. - Hassan Salmani; Mohammad Tehranipoor; Jim Plusquellic (HOST, 2009)

Characterizing within-die variation from multiple supply port IDDQ measurements. - Kanak Agarwal 001; Dhruva Acharyya; Jim Plusquellic (ICCAD, 2009)

A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals. - Reza M. Rad; Jim Plusquellic (J. Electron. Test., 2009)

Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. - Ryan Helinski; Dhruva Acharyya; Jim Plusquellic (DAC, 2010)

Leveraging existing power control circuits and power delivery architecture for variability measurement. - Dhruva Acharyya; Kanak Agarwal 001; Jim Plusquellic (ITC, 2010)

A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits. - Hassan Salmani; Mohammad Tehranipoor; Jim Plusquellic (WIFS, 2010)

Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. - Jim Aarestad; Dhruva Acharyya; Reza M. Rad; Jim Plusquellic (IEEE Trans. Inf. Forensics Secur., 2010)

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions. - Reza M. Rad; James F. Plusquellic; Mohammad Tehranipoor (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. - Jim Aarestad; Charles Lamech; Jim Plusquellic; Dhruva Acharyya; Kanak Agarwal 001 (DAC, 2011)

REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. - Charles Lamech; Jim Aarestad; Jim Plusquellic; Reza M. Rad; Kanak Agarwal 001 (ICCAD, 2011)

Measuring within-die spatial variation profile through power supply current measurements. - Jim Plusquellic; Dhruva Acharyya; Kanak Agarwal 001 (ISQED, 2011)

An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities. - Charles Lamech; Reza M. Rad; Mohammad Tehranipoor; Jim Plusquellic (IEEE Trans. Inf. Forensics Secur., 2011)

Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors. - Jing Ju; Jim Plusquellic; Raj Chakraborty; Reza M. Rad (HOST, 2012)

Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure. - Charles Lamech; Jim Plusquellic (HOST, 2012)

Securing Trusted Execution Environments with PUF Generated Secret Keys. - Matthew Areno; Jim Plusquellic (TrustCom, 2012)

A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. - Hassan Salmani; Mohammad Tehranipoor; Jim Plusquellic (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. - Raj Chakraborty; Charles Lamech; Dhruva Acharyya; Jim Plusquellic (DAC, 2013)

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. - Jim Aarestad; Jim Plusquellic; Dhruva Acharyya (HOST, 2013)

Stability analysis of a physical unclonable function based on metal resistance variations. - J. Ju; Ray Chakraborty; Charles Lamech; Jim Plusquellic (HOST, 2013)

Secure mobile authentication and device association with enhanced cryptographic engines. - Matthew Areno; James F. Plusquellic (PRISMS, 2013)

HELP: A Hardware-Embedded Delay PUF. - Jim Aarestad; Philip Ortiz; Dhruva Acharyya; Jim Plusquellic (IEEE Des. Test, 2013)

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. - Swarup Bhunia; Miron Abramovici; Dakshi Agrawal; Paul Bradley; Michael S. Hsiao; Jim Plusquellic; Mohammad Tehranipoor (IEEE Des. Test, 2013)

IP-level implementation of a resistance-based physical unclonable function. - Dylan Ismari; Jim Plusquellic (HOST, 2014)

A non-volatile memory based physically unclonable function without helper data. - Wenjie Che; Jim Plusquellic; Swarup Bhunia (ICCAD, 2014)

ASIC implementation of a hardware-embedded physical unclonable function. - Fareena Saqib; Matthew Areno; Jim Aarestad; James F. Plusquellic (IET Comput. Digit. Tech., 2014)

Cyber-physical systems: A security perspective. - Charalambos Konstantinou; Michail Maniatakos; Fareena Saqib; Shiyan Hu 001; Jim Plusquellic; Yier Jin (ETS, 2015)

GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units. - Ian Wilcox; Fareena Saqib; James F. Plusquellic (HOST, 2015)

PUF-Based Authentication. - Wenjie Che; Fareena Saqib; Jim Plusquellic (ICCAD, 2015)

Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). - Fareena Saqib; Aindrik Dutta; Jim Plusquellic; Philip Ortiz; Marios S. Pattichis (IEEE Trans. Computers, 2015)

Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. - Fareena Saqib; Dylan Ismari; Charles Lamech; Jim Plusquellic (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Current based PUF exploiting random variations in SRAM cells. - Fengchao Zhang; Shuo Yang; Jim Plusquellic; Swarup Bhunia (DATE, 2016)

On detecting delay anomalies introduced by hardware trojans. - Dylan Ismari; Jim Plusquellic; Charles Lamech; Swarup Bhunia; Fareena Saqib (ICCAD, 2016)

Poster: Hardware based security enhanced framework for automotives. - Ali Shuja Siddiqui; Yutian Gui; Jim Plusquellic; Fareena Saqib (VNC, 2016)

Secure intra-vehicular communication over CANFD. - Ali Shuja Siddiqui; Chia-Che Lee; Wenjie Che; Jim Plusquellic; Fareena Saqib (AsianHOST, 2017)

A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF. - Wenjie Che; Jim Plusquellic; Fareena Saqib (HOST, 2017)

Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems. - Goutham Pocklassery; Venkata K. Kajuruli; James F. Plusquellic; Fareena Saqib (HOST, 2017)

Secure communication over CANBus. - Ali Shuja Siddiqui; Yutian Gui; Jim Plusquellic; Fareena Saqib (MWSCAS, 2017)

Analysis of Entropy in a Hardware-Embedded Delay PUF. - Wenjie Che; Venkata K. Kajuluri; Mitchell T. Martin; Fareena Saqib; Jim Plusquellic (Cryptogr., 2017)

Leveraging Distributions in Physical Unclonable Functions. - Wenjie Che; Venkata K. Kajuluri; Fareena Saqib; Jim Plusquellic (Cryptogr., 2017)

A Privacy-Preserving, Mutual PUF-Based Authentication Protocol. - Wenjie Che; Mitchell T. Martin; Goutham Pocklassery; Venkata K. Kajuluri; Fareena Saqib; Jim Plusquellic (Cryptogr., 2017)

Delay model and machine learning exploration of a hardware-embedded delay PUF. - Wenjie Che; Manel Martínez-Ramón; Fareena Saqib; Jim Plusquellic (HOST, 2018)

Self-authenticating secure boot for FPGAs. - Goutham Pocklassery; Wenjie Che; Fareena Saqib; Matthew Areno; Jim Plusquellic (HOST, 2018)

Hardware Assisted Security Architecture for Smart Grid. - Ali Shuja Siddiqui; Yutian Gui; David Lawrence; Stuart Laval; Jim Plusquellic; Madhav D. Manjrekar; Badrul H. Chowdhury; Fareena Saqib (IECON, 2018)

An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays. - Don Owen Jr.; Derek Heeger; Calvin Chan; Wenjie Che; Fareena Saqib; Matthew Areno; Jim Plusquellic (Cryptogr., 2018)

Correlation-Based Robust Authentication (Cobra) Using Helper Data Only. - Jim Plusquellic; Matthew Areno (Cryptogr., 2018)

Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. - Wenjie Che; Fareena Saqib; Jim Plusquellic (IEEE Trans. Very Large Scale Integr. Syst., 2018)

IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future. - Domenic Forte; Swarup Bhunia; Ramesh Karri; Jim Plusquellic; Mark Tehranipoor (ITC, 2019)

Secure Design Flow of FPGA Based RISC-V Implementation. - Ali Shuja Siddiqui; Geraldine Shirley; Shreya Bendre; Girija Bhagwat; Jim Plusquellic; Fareena Saqib (IVSW, 2019)

Multilayer Camouflaged Secure Boot for SoCs. - Ali Shuja Siddiqui; Geraldine Shirley; Sam Reji Joseph; Yutian Gui; Jim Plusquellic; Marten van Dijk; Fareena Saqib (MTV, 2019)

Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash). - Jeff Calhoun; Cyrus Minwalla; Charles Helmich; Fareena Saqib; Wenjie Che; Jim Plusquellic (Cryptogr., 2019)

Secure Energy Constrained LoRa Mesh Network. - Derek Heeger; Maeve Garigan; Eirini-Eleni Tsiropoulou; Jim Plusquellic (ADHOC-NOW, 2020)

Analysis of IoT Authentication Over LoRa. - Derek Heeger; Jim Plusquellic (DCOSS, 2020)

UAV-enabled Human Internet of Things. - Kelly Rael; Georgios Fragkos; Jim Plusquellic; Eirini-Eleni Tsiropoulou (DCOSS, 2020)

Adaptive Data Rate Techniques for Energy Constrained Ad Hoc LoRa Networks. - Derek Heeger; Maeve Garigan; Jim Plusquellic (GIoTS, 2020)

Reinforcement Learning Toward Decision-Making for Multiple Trusted-Third-Parties in PUF-Cash. - Georgios Fragkos; Cyrus Minwalla; Jim Plusquellic; Eirini-Eleni Tsiropoulou (WF-IoT, 2020)

Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. - Ivan Bow; Nahome Bete; Fareena Saqib; Wenjie Che; Chintan Patel; Ryan W. Robucci; Calvin Chan; Jim Plusquellic (Cryptogr., 2020)

NotchPUF: Printed Circuit Board PUF Based on Microstrip Notch Filter. - Mitchell T. Martin; Jim Plusquellic (Cryptogr., 2020)

Artificially Intelligent Electronic Money. - Georgios Fragkos; Cyrus Minwalla; Jim Plusquellic; Eirini-Eleni Tsiropoulou (IEEE Consumer Electron. Mag., 2021)

Secure LoRa Firmware Update with Adaptive Data Rate Techniques. - Derek Heeger; Maeve Garigan; Eirini-Eleni Tsiropoulou; Jim Plusquellic (Sensors, 2021)

Network Economics-based Crowdsourcing in UAV-assisted Smart Cities Environments. - Fisayo Sangoleye; Md Sahabul Hossain; Eirini-Eleni Tsiropoulou; Jim Plusquellic (DCOSS, 2022)

True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF. - Nafis Irtija; Eirini-Eleni Tsiropoulou; Cyrus Minwalla; Jim Plusquellic (HOST, 2022)

Reconfigurable Intelligent Surfaces enabling Positioning, Navigation, and Timing Services. - Md Sahabul Hossain; Nafis Irtija; Eirini-Eleni Tsiropoulou; Jim Plusquellic; Symeon Papavassiliou (ICC, 2022)

Orchestration of Reconfigurable Intelligent Surfaces for Positioning, Navigation, and Timing. - Md. Sadman Siraj; Aisha B. Rahman; Maria Diamanti; Eirini-Eleni Tsiropoulou; Symeon Papavassiliou; Jim Plusquellic (MILCOM, 2022)

Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing. - Nafis Irtija; Jim Plusquellic; Eirini-Eleni Tsiropoulou; Joshua Goldberg; Daniel S. Lobser; Daniel Stick (CoRR, 2022)

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor. - Donald E. Owen; Jithin Joseph; Jim Plusquellic; Tom J. Mannos; Brian Dziki (Cryptogr., 2022)

Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA. - Jim Plusquellic (Cryptogr., 2022)

Enhancing Privacy in PUF-Cash through Multiple Trusted Third Parties and Reinforcement Learning. - Georgios Fragkos; Cyrus Minwalla; Eirini-Eleni Tsiropoulou; Jim Plusquellic (ACM J. Emerg. Technol. Comput. Syst., 2022)

Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things. - Saraju P. Mohanty; Jim Plusquellic; Garrett S. Rose; Wei Zhang 012; Maria K. Michael (ACM J. Emerg. Technol. Comput. Syst., 2022)

Local Trust in Internet of Things Based on Contract Theory. - Georgios Fragkos; Cyrus Minwalla; Jim Plusquellic; Eirini-Eleni Tsiropoulou (Sensors, 2022)

Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. - Jim Plusquellic; Donald E. Owen; Tom J. Mannos; Brian Dziki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Symbiotic Positioning, Navigation, and Timing. - Md. Sadman Siraj; Aisha B. Rahman; Eirini-Eleni Tsiropoulou; Symeon Papavassiliou; Jim Plusquellic (DCOSS-IoT, 2023)

SAFE: Secure Symbiotic Positioning, Navigation, and Timing. - Md. Sadman Siraj; Eirini-Eleni Tsiropoulou; Symeon Papavassiliou; Jim Plusquellic (GLOBECOM, 2023)

Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF. - Jim Plusquellic; Eirini-Eleni Tsiropoulou; Cyrus Minwalla (IEEE Trans. Emerg. Top. Comput., 2023)

An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. - Jenilee Jao; Ian Wilcox; Sriram Thotakura; Calvin Chan; Jim Plusquellic; Biliana S. Paskaleva; Pavel B. Bochev (J. Hardw. Syst. Secur., 2023)

Correction to: An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. - Jenilee Jao; Ian Wilcox; Sriram Thotakura; Calvin Chan; Jim Plusquellic; Biliana S. Paskaleva; Pavel B. Bochev (J. Hardw. Syst. Secur., 2023)

Statistical Quality Comparison of the Bitstrings Generated by a Physical Unclonable Function across Xilinx, Altera and Microsemi Devices. - Jenilee Jao; Kristi Hoffman; Cheryl Reid; Ryan Thomson; Michael Thompson; Jim Plusquellic (CoRR, 2024)

A Physical Layer Analysis of Entropy in Delay-Based PUFs Implemented on FPGAs. - Jim Plusquellic; Jennifer Howard; Ross MacKinnon; Kristianna Hoffman; Eirini-Eleni Tsiropoulou; Calvin Chan (CoRR, 2024)

Lightweight Mutually Authenticated Key Exchange with Physical Unclonable Functions. - Cyrus Minwalla; Jim Plusquellic; Eirini Eleni Tsiropoulou (Cryptogr., 2024)

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. - Idris Somoye; Jim Plusquellic; Tom J. Mannos; Brian Dziki (Cryptogr., 2024)

Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. - Idris Somoye; Tom J. Mannos; Brian Dziki; Jim Plusquellic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PUF-based Digital Money with Propagation-of-Provenance and Offline Transfers between Two Parties. - Benjamin Bean; Cyrus Minwalla; Eirini-Eleni Tsiropoulou; Jim Plusquellic (ACM J. Emerg. Technol. Comput. Syst., 2024)

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions. - Jenilee Jao; Ian Wilcox; Jim Plusquellic; Biliana S. Paskaleva; Pavel B. Bochev (Cryptogr., 2024)

Sourcing Trust From Peers with Physical Unclonable Functions. - Md. Sadman Siraj; Aisha B. Rahman; Cyrus Minwalla; Eirini Eleni Tsiropoulou; Jim Plusquellic (HOST, 2025)

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures. - Priya A. Bhakta; Jim Plusquellic; Andrew Suchanek; Tom J. Mannos (IEEE Access, 2025)

Symbiotic Positioning, Navigation, and Timing via Game Theory and Reinforcement Learning. - Md. Sadman Siraj; Eirini Eleni Tsiropoulou; Symeon Papavassiliou; Jim Plusquellic (IEEE Access, 2025)

A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture. - Rachel Cazzola; Cyrus Minwalla; Calvin Chan; Jim Plusquellic (CoRR, 2025)