An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. - Jeff L. Sonntag; John T. Stonick; James Gorecki; Bill Beale; Bill Check; Xue-Mei Gong; Joe Guiliano; Kyong Lee; Bob Lefferts; David A. Yokoyama-Martin; Un-Ku Moon; Amber Sengir; et al. (CICC, 2002)

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS. - Karthik Gopalakrishnan; Alan Ren; Amber Tan; Arash Farhood; Arun Tiruvur; Belal Helal; Chang-Feng Loi; Chris Jiang; Halil Cirit; Irene Quek; Jamal Riani; James Gorecki; et al. (ISSCC, 2016)

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS. - Michael Q. Le; James Gorecki; Jamal Riani; Jorge Pernillo; A. Tan; K. Gopalakrishnan; Belal Helal; Pulkit Khandelwal; Chang-Feng Loi; Irene Quek; P. Wong; Aaron Buchwald (CICC, 2017)