A Figure of Merit for Single-Pass Data Recording Systems. - James H. Mulligan Jr. (IRE Trans. Electron. Comput., 1959)

Two coding strategies for bidirectional associative memory. - Yeou-Fang Wang; Jose B. Cruz Jr.; James H. Mulligan Jr. (IEEE Trans. Neural Networks, 1990)

On multiple training for bidirectional associative memory. - Yeou-Fang Wang; Jose B. Cruz Jr.; James H. Mulligan Jr. (IEEE Trans. Neural Networks, 1990)

Guaranteed recall of all training pairs for bidirectional associative memory. - Yeou-Fang Wang; Jose B. Cruz Jr.; James H. Mulligan Jr. (IEEE Trans. Neural Networks, 1991)

Clock frequency and latency in synchronous digital systems. - Eby G. Friedman; James H. Mulligan Jr. (IEEE Trans. Signal Process., 1991)

Integration of Clock Skew and Register Delays into a Retiming Algorithm. - Tolga Soyata; Eby G. Friedman; James H. Mulligan Jr. (ISCAS, 1993)

Multiple training concept for back-propagation neural networks for use in associative memories. - Yeou-Fang Wang; Jose B. Cruz Jr.; James H. Mulligan Jr. (Neural Networks, 1993)

Optimization of phase-locked loop performance in data recovery systems. - Ramon S. Co; James H. Mulligan Jr. (IEEE J. Solid State Circuits, 1994)

Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. - Tolga Soyata; Eby G. Friedman; James H. Mulligan Jr. (ISCAS, 1995)

Incorporating interconnect, register, and clock distribution delays into the retiming process. - Tolga Soyata; Eby G. Friedman; James H. Mulligan Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)