: A Testable PLA Design with Minimal Hardware and Test Set. - James Jacob; Nripendra N. Biswas (ITC, 1985)

Further Comments on "Detection of Faults in Programmable Logic Arrays". - James Jacob; Nripendra N. Biswas (IEEE Trans. Computers, 1990)

Finite State Machine Testing Based on Growth and Dissappearance Faults. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (FTCS, 1992)

Functional Test Generation for Sequential Circuits. - James Jacob; Vishwani D. Agrawal (VLSI Design, 1992)

An Efficient Rule Based Fault Simulator. - Oommen Tharakan; James Jacob; Mandyam-Komar Srinivas (VLSI Design, 1992)

Multiple fault detection in two-level multi-output circuits. - James Jacob; Vishwani D. Agrawal (J. Electron. Test., 1992)

Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. - P. R. Suresh Kumar; Mandyam-Komar Srinivas; James Jacob (VLSI Design, 1993)

An Improved Deductive Fault Simulator. - P. R. Suresh Kumar; James Jacob; Mandyam-Komar Srinivas; Vishwani D. Agrawal (VLSI Design, 1994)

Logic minimization based approach for compressing image data. - Jacob Augustine; Wen Feng; James Jacob (VLSI Design, 1995)

An efficient automatic test generation system for path delay faults in combinational circuits. - Ananta K. Majhi; James Jacob; Lalit M. Patnaik; Vishwani D. Agrawal (VLSI Design, 1995)

Functional test generation for non-scan sequential circuits. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (VLSI Design, 1995)

Switching theoretic approach to image compression. - Jacob Augustine; Wen Feng; Anamitra Makur; James Jacob (Signal Process., 1995)

Lossless Compression Of Images Using Logic Minimization. - Anil K. Chaudhay; Jacob Augustine; James Jacob (ICIP (1), 1996)

Cubical CAMP for minimization of Boolean functions. - Nripendra N. Biswas; C. Srikanth; James Jacob (VLSI Design, 1996)

On test coverage of path delay faults. - Ananta K. Majhi; James Jacob; Lalit M. Patnaik; Vishwani D. Agrawal (VLSI Design, 1996)

Functional test generation for synchronous sequential circuits. - Mandyam-Komar Srinivas; James Jacob; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A Novel Path Delay Fault Simulator Using Binary Logic. - Ananta K. Majhi; James Jacob; Lalit M. Patnaik (VLSI Design, 1996)

Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. - James Jacob; P. Srinivas Sivakumar; Vishwani D. Agrawal (VLSI Design, 1997)

Optimizing Logic Design Using Boolean Transforms. - Pramit Chavda; James Jacob; Vishwani D. Agrawal (VLSI Design, 1998)

A Fast Two-level Logic Minimizer. - P. Srinivasa Rao; James Jacob (VLSI Design, 1998)

Line coverage of path delay faults. - Ananta K. Majhi; V. D. Agrawak; James Jacob; Lalit M. Patnaik (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Improving spatial transferability of ecological niche model of Hevea brasiliensis using pooled occurrences of introduced ranges in two biogeographic regions of India. - Debabrata Ray; Mukunda Dev Behera; James Jacob (Ecol. Informatics, 2016)