Working group report on environments [program environments]. - James Myers; John Callahan (WETICE, 1995)

MiniJudge: Software for minimalist experimental syntax. - James Myers (ROCLING, 2006)

MiniJudge: Software for Small-Scale Experimental Syntax. - James Myers (Int. J. Comput. Linguistics Chin. Lang. Process., 2007)

Lexical frequency effects in Taiwan Southern Min syllable contraction. - James Myers; Yingshing Li (J. Phonetics, 2009)

Syntactic Judgment Experiments. - James Myers (Lang. Linguistics Compass, 2009)

Cognitive Styles in Two Cognitive Sciences. - James Myers (CogSci, 2012)

Grammatical Approaches to Written and Graphical Communication. - Colin Wilson; Neil Cohn; James Myers; Stephen Goldberg; Ariel Cohen-Goldberg (CogSci, 2012)

dRail: A Novel Physical Layout Methodology for Power Gated Circuits. - Jatin N. Mistry; John Biggs; James Myers; Bashir M. Al-Hashimi; David Flynn (PATMOS, 2012)

Development and Testing of Transcription Software for a Southern Min Spoken Corpus. - Jia-Cing Ruan; Chiung-Wen Hsu; James Myers; Jane S. Tsay (Int. J. Comput. Linguistics Chin. Lang. Process., 2012)

Keynote & invited speaker's biography [7 biographies]. - Bert Gyselinckx; Hiroshi Kanayama; Michael McCool; Shintaro Momose; Takeshi Kataoka; James Myers; Toshio Yoshida (COOL Chips, 2013)

Panel discussions the next step in processor evolution. - Yoshio Masubuchi; Bert Gyselinckx; Michael McCool; Shintaro Momose; James Myers; Toshio Yoshida (COOL Chips, 2013)

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Tatsuya Onuki; Wataru Uesugi; Takuro Ohmaru; Kazuaki Ohshima; Hidetomo Kobayashi; Seiichi Yoneda; Atsuo Isobe; Naoaki Tsutsui; Suguru Hondo; et al. (COOL Chips, 2014)

Clock-modulation based watermark for protection of embedded processors. - Jedrzej Kufel; Peter R. Wilson; Stephen Hill; Bashir M. Al-Hashimi; Paul N. Whatmough; James Myers (DATE, 2014)

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Wataru Uesugi; Atsuo Isobe; Naoaki Tsutsui; Yasutaka Suzuki; Yutaka Okazaki; Yukio Maehashi; Jun Koyama; Yoshitaka Yamamoto; Shunpei Yamazaki; et al. (IEEE Micro, 2014)

Active Mode Subclock Power Gating. - Jatin N. Mistry; James Myers; Bashir M. Al-Hashimi; David Flynn; John Biggs; Geoff V. Merrett (IEEE Trans. Very Large Scale Integr. Syst., 2014)

8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. - James Myers; Anand Savanth; David Howard; Rohan Gaddh; Pranay Prabhat; David Flynn (ISSCC, 2015)

Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design. - Anand Savanth; Alex S. Weddell; James Myers; David Flynn; Bashir M. Al-Hashimi (ENSsys@SenSys, 2015)

Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem. - James Myers; Pranay Prabhat; Anand Savanth; Sheng Yang; Rohan Gaddh (PATMOS, 2016)

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. - Tatsuya Onuki; Wataru Uesugi; Hikaru Tamura; Atsuo Isobe; Yoshinori Ando; Satoru Okamoto; Kiyoshi Kato; Tri Rung Yew; Chen Bin Lin; J. Y. Wu; Chi Chang Shuai; Shao Hui Wu; et al. (VLSI Circuits, 2016)

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator. - James Myers; Anand Savanth; Rohan Gaddh; David Howard; Pranay Prabhat; David Flynn (IEEE J. Solid State Circuits, 2016)

Session 3 overview: Digital processors. - Thomas Burd; James Myers; Byeong-Gyu Nam (ISSCC, 2017)

5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability. - Anand Savanth; James Myers; Alex S. Weddell; David Flynn; Bashir M. Al-Hashimi (ISSCC, 2017)

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library. - Jordan Morris; Pranay Prabhat; James Myers; Alex Yakovlev (ISVLSI, 2017)

Evaluation and analysis of single-phase clock flip-flops for NTV applications. - Yunpeng Cai; Anand Savanth; Pranay Prabhat; James Myers; Alex S. Weddell; Tom J. Kazmierski (PATMOS, 2017)

A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems. - Anand Savanth; Alex S. Weddell; James Myers; David Flynn; Bashir M. Al-Hashimi (VLSID, 2017)

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. - Tatsuya Onuki; Wataru Uesugi; Atsuo Isobe; Yoshinori Ando; Satoru Okamoto; Kiyoshi Kato; Tri Rung Yew; J. Y. Wu; Chi Chang Shuai; Shao Hui Wu; James Myers; Klaus Doppler; et al. (IEEE J. Solid State Circuits, 2017)

Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems. - Anand Savanth; Alex S. Weddell; James Myers; David Flynn; Bashir M. Al-Hashimi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup. - Pranay Prabhat; Graham Knight; Supreet Jeloka; Sheng Yang; James Myers (A-SSCC, 2018)

F1: Intelligent energy-efficient systems at the edge of IoT. - Vivek De; Dennis Sylvester; James Myers; Jun Deguchi; Shinichiro Shiratake; Ingrid Verbauwhede (ISSCC, 2018)

Communicative Efficiency in Child Mandarin. - Jane S. Tsay; James Myers (PACLIC, 2018)

A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing. - Philex Ming-Yan Fan; Anand Savanth; Benoît Labbé; Pranay Prabhat; James Myers (ESSCIRC, 2019)

A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy. - Supreet Jeloka; Pranay Prabhat; Graham Knight; James Myers (ISLPED, 2019)

Simple, Standards-based Archiving in Dataverse. - James Myers; Sebastian Karcher; Sebastian Ostrowski; Nic Weber (RO, 2019)

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. - Yunpeng Cai; Anand Savanth; Pranay Prabhat; James Myers; Alex S. Weddell; Tom J. Kazmierski (IEEE J. Solid State Circuits, 2019)

A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator. - Anand Savanth; Alex S. Weddell; James Myers; David Flynn; Bashir M. Al-Hashimi (IEEE J. Solid State Circuits, 2019)

27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power. - Pranay Prabhat; Benoît Labbé; Graham Knight; Anand Savanth; Jonas Svedas; Matthew J. Walker; Supreet Jeloka; Philex Ming-Yan Fan; Fernando García-Redondo; Thanusree Achuthan; James Myers (ISSCC, 2020)

A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller. - Benoît Labbé; Philex Ming-Yan Fan; Thanusree Achuthan; Pranay Prabhat; Graham Knight; James Myers (IEEE J. Solid State Circuits, 2021)

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. - Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José María Llabería; James Myers; Julien Ryckaert; Dwaipayan Biswas; Francky Catthoor (ICECS, 2023)

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). - Subrat Mishra; Sankatali Venkateswarlu; Bjorn Vermeersch; Moritz Brunion; Melina Lofrano; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Gaspard Hiblot; Geert Van der Plas; Pieter Weckx; et al. (IRPS, 2023)

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. - Nitish Kumar; Sankatali Venkateswarlu; Yukai Chen; Moritz Brunion; Subrat Mishra; Ankur Gupta; Pushpapraj Singh; Francky Catthoor; James Myers; Julien Ryckaert; Dwaipayan Biswas (IRPS, 2024)

Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. - Subrat Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; A. Sharma; G. Mirabeli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; et al. (IRPS, 2024)

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. - Sudipta Das; Samuel Riedel; Marco Bertuletti; Luca Benini; Moritz Brunion; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (ISCAS, 2024)

STCO: Driving the More than Moore Era. - Dwaipayan Biswas; James Myers; Srikanth B. Samavedam; Julien Ryckaert (ISVLSI, 2024)

Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet. - Yukai Chen; Sankatali Venkateswarlu; Subrat Mishra; Julien Ryckaert; James Myers; Dwaipayan Biswas (ISVLSI, 2024)

Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. - Aakash Patel; Dwaipayan Biswas; Joyjit Kundu; Yoojin Ban; Nicolas Pantano; Arindam Mallik; Julien Ryckaert; James Myers (ISVLSI, 2024)

On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. - Siva Satyendra Sahoo; Dawit Burusie Abdi; Julien Ryckaert; James Myers; Dwaipayan Biswas (SOCC, 2024)

Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). - S. Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; Gioele Mirabelli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Francky Catthoor; et al. (VLSI Technology and Circuits, 2024)

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. - Zhenlin Pei; Hsiao-Hsuan Liu; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Zsolt Tokei; Dawit Burusie Abdi; James Myers; Chenyun Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. - Leandro Mateus Giacomini Rocha; Refik Bilgic; Mohamed Naeim; Sudipta Das; Herman Oprins; Amirreza Yousefzadeh; Mario Konijnenburg; Dragomir Milojevic; James Myers; Julien Ryckaert; Dwaipayan Biswas (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology. - Yukai Chen; Subrat Mishra; Julien Ryckaert; Dwaipayan Biswas; James Myers (DATE, 2025)

Framework for Augmenting Main Memory with CXL-connected Emerging Memory Alternatives. - Khakim Akhunov; Dwaipayan Biswas; Emil Karimov; Arvind Sharma; Hyungrock Oh; Maarten Rosmeulen; Julien Ryckaert; James Myers (ISCAS, 2025)

3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology. - Bhawana Kumari; Anurag Swarnkar; Dawit Burusie Abdi; Fernando García-Redondo; James Myers; Julien Ryckaert; Jaydeep Kulkarni; Dwaipayan Biswas (ISCAS, 2025)

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. - Sudipta Das; Samuel Riedel; Mohamed Naeim; Moritz Brunion; Marco Bertuletti; Luca Benini; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (IEEE Trans. Very Large Scale Integr. Syst., 2025)

TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering. - Sangmin Yoo; Amod Holla; Sourav Sanyal; Dong Eun Kim; Francesca Iacopi; Dwaipayan Biswas; James Myers; Kaushik Roy 001 (CoRR, 2025)

A Survey of End-to-End Modeling for Distributed DNN Training: Workloads, Simulators, and TCO. - Jonas Svedas; Hannah Watson; Nathan Laubeuf; Diksha Moolchandani; Abubakr Nada; Arjun Singh; Dwaipayan Biswas; James Myers; Debjyoti Bhattacharjee (CoRR, 2025)

Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology. - Yukai Chen; Massimiliano Di Todaro; Bjorn Vermeersch; Herman Oprins; Daniele Jahier Pagliari; Julien Ryckaert; Dwaipayan Biswas; James Myers (CoRR, 2025)