A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. - Gianfranco Gerosa; Mike Alexander; Jose Alvarez; Cody Croxton; Michael D'Addeo; A. Richard Kennedy; Carmine Nicoletta; James P. Nissen; Ross Philip; Paul Reed; Hector Sanchez; Scott A. Taylor; et al. (IEEE J. Solid State Circuits, 1997)

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology. - Hector Sanchez; Joshua Siegel; Carmine Nicoletta; James P. Nissen; José Alvarez (IEEE J. Solid State Circuits, 1999)