A wafer scale integration systolic processor for connected word recognition. - Joel A. Feldman; Steven L. Garverick; F. Matthew Rhodes; James R. Mann (ICASSP, 1984)

A wafer scale DTW multiprocessor. - James R. Mann; F. Matthew Rhodes (ICASSP, 1986)

An Analog Self-Organizing Neural Network Chip. - James R. Mann; Sheldon Gilbert (NIPS, 1988)