A Clock Duty-Cycle Correction and Adjustment Circuit. - James S. Humble; Patrick J. Zabinski; Barry K. Gilbert; Erik S. Daniel (ISSCC, 2006)

A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS. - Rick A. Philpott; James S. Humble; Robert A. Kertis; Karl E. Fritz; Barry K. Gilbert; Erik S. Daniel (CICC, 2008)

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators. - Robert A. Kertis; James S. Humble; Mary A. Daun-Lindberg; Rick A. Philpott; Karl E. Fritz; Daniel J. Schwab; Jason F. Prairie; Barry K. Gilbert; Erik S. Daniel (IEEE J. Solid State Circuits, 2009)