An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. - Michael Cogswell; Don Pearl; James Sage; Alan Troidl (ICCD, 2000)

Test structure verification of logical BIST: problems and solutions. - Michael Cogswell; Don Pearl; James Sage; Alan Troidl (ITC, 2000)

Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns. - Gaurav Bhargava; Dale Meehl; James Sage (ITC, 2007)

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. - Vivek Chickermane; Patrick R. Gallagher Jr.; James Sage; Paul Yuan; Krishna Chakravadhanula (ITC, 2008)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)