Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology. - James T. Kao; Anantha P. Chandrakasan; Dimitri A. Antoniadis (DAC, 1997)

MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. - James T. Kao; Siva G. Narendra; Anantha P. Chandrakasan (DAC, 1998)

Dual-threshold voltage techniques for low-power digital circuits. - James T. Kao; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2000)

Subthreshold leakage control techniques for low power digital circuits. - James T. Kao (2001)

Subthreshold leakage modeling and reduction techniques. - James T. Kao; Siva G. Narendra; Anantha P. Chandrakasan (ICCAD, 2002)

A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. - James T. Kao; Masayuki Miyazaki; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2002)

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. - James W. Tschanz; James T. Kao; Siva G. Narendra; Raj Nair; Dimitri A. Antoniadis; Anantha P. Chandrakasan; Vivek De (IEEE J. Solid State Circuits, 2002)

A Fully Integrated 0.13-µm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. - Adrian Maxim; Ramin K. Poorfard; Richard A. Johnson; Philip John Crawley; James T. Kao; Zhiwei Dong; Madhu Chennam; Tim Nutt; David S. Trager (IEEE J. Solid State Circuits, 2007)

A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration. - Adrian Maxim; Ramin K. Poorfard; Richard A. Johnson; Philip John Crawley; James T. Kao; Zhiwei Dong; Madhu Chennam; Tim Nutt; David S. Trager; Mitchell Reid (IEEE J. Solid State Circuits, 2007)

A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities. - Adrian Maxim; Ramin Khoini-Poorfard; Mitchell Reid; James T. Kao; Charles D. Thompson; Richard A. Johnson (ISSCC, 2008)