A Common Runtime for High Performance Data Analysis. - Shoumik Palkar; James Thomas 003; Anil Shanbhag; Deepak Narayanan; Holger Pirk; Malte Schwarzkopf; Saman P. Amarasinghe; Matei Zaharia (CIDR, 2017)

Weld: Rethinking the Interface Between Data-Intensive Applications. - Shoumik Palkar; James Thomas 003; Deepak Narayanan; Anil Shanbhag; Rahul Palamuttam; Holger Pirk; Malte Schwarzkopf; Saman P. Amarasinghe; Samuel Madden 001; Matei Zaharia (CoRR, 2017)

Laika: Efficient In-Place Scheduling for 3D Mesh Graph Computations. - Predrag Gruevski; William Hasenplaugh; David Lugato; James Thomas 003 (SPAA, 2018)

Evaluating End-to-End Optimization for Data Analytics Applications in Weld. - Shoumik Palkar; James Thomas 003; Deepak Narayanan; Pratiksha Thaker; Rahul Palamuttam; Parimarjan Negi; Anil Shanbhag; Malte Schwarzkopf; Holger Pirk; Saman P. Amarasinghe; Samuel Madden 001; Matei Zaharia (Proc. VLDB Endow., 2018)

Optimizing DNN Computation with Relaxed Graph Substitutions. - Zhihao Jia; James Thomas 003; Todd Warszawski; Mingyu Gao 001; Matei Zaharia; Alex Aiken (SysML, 2019)

TASO: optimizing deep learning computation with automatic generation of graph substitutions. - Zhihao Jia; Oded Padon; James Thomas 003; Todd Warszawski; Matei Zaharia; Alex Aiken (SOSP, 2019)

Fleet: A Framework for Massively Parallel Streaming on FPGAs. - James Thomas 003; Pat Hanrahan; Matei Zaharia (ASPLOS, 2020)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

Software-like Compilation for Data Center FPGA Accelerators. - James Thomas 003; Chris Lavin; Alireza Kaviani (HEART, 2021)

Enabling Reusable Physical Design Flows with Modular Flow Generators. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (CoRR, 2021)

mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (DAC, 2022)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)