A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (ISSCC, 2018)

A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. - Zheng Guo; Daeyeon Kim; Satyanand Nalam; Jami Wiedemer; Xiaofei Wang; Eric Karl (IEEE J. Solid State Circuits, 2019)

A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. - Zheng Guo; Jami Wiedemer; Yusung Kim 002; Prithvee Sundararajan Ramamoorthy; Prateeksha Bindiganavile Sathyaprasad; Smita Shridharan; Daeyeon Kim; Eric Karl (VLSI Circuits, 2020)