Hardware Identification of Cache Conflict Misses. - Jamison D. Collins; Dean M. Tullsen (MICRO, 1999)

Speculative precomputation: long-range prefetching of delinquent loads. - Jamison D. Collins; Hong Wang 003; Dean M. Tullsen; Christopher J. Hughes; Yong-Fong Lee; Daniel M. Lavery; John Paul Shen (ISCA, 2001)

Dynamic speculative precomputation. - Jamison D. Collins; Dean M. Tullsen; Hong Wang 003; John Paul Shen (MICRO, 2001)

Runtime identification of cache conflict misses: The adaptive miss buffer. - Jamison D. Collins; Dean M. Tullsen (ACM Trans. Comput. Syst., 2001)

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. - Perry H. Wang; Hong Wang 003; Jamison D. Collins; Ed Grochowski; Ralph-Michael Kling; John Paul Shen (HPCA, 2002)

Pointer cache assisted prefetching. - Jamison D. Collins; Suleyman Sair; Brad Calder; Dean M. Tullsen (MICRO, 2002)

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (ASPLOS, 2004)

Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time. - Jamison D. Collins; Dean M. Tullsen (IPDPS, 2004)

Control Flow Optimization Via Dynamic Reconvergence Prediction. - Jamison D. Collins; Dean M. Tullsen; Hong Wang 003 (MICRO, 2004)

Helper Threads via Virtual Multithreading. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (IEEE Micro, 2004)

Multiple Instruction Stream Processor. - Richard A. Hankins; Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Ryan N. Rakvic; Hong Wang 003; John Paul Shen (ISCA, 2006)

Sequencer virtualization. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Bernard Lint; Asit Mallick; Koichi Yamada; Hong Wang 003 (ICS, 2007)

EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Hong Jiang; Xinmin Tian; Milind Girkar; Nick Y. Yang; Guei-Yuan Lueh; Hong Wang 003 (PLDI, 2007)

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. - Henry Wong; Anne Bracy; Ethan Schuchman; Tor M. Aamodt; Jamison D. Collins; Perry H. Wang; Gautham N. Chinya; Ankur Khandelwal Groen; Hong Jiang; Hong Wang 003 (PACT, 2008)

Merge: a programming model for heterogeneous multi-core systems. - Michael D. Linderman; Jamison D. Collins; Hong Wang 003; Teresa H. Meng (ASPLOS, 2008)

Processor Performance Modeling using Symbolic Simulation. - Omid Azizi; Jamison D. Collins; Dinesh Patil; Hong Wang 003; Mark Horowitz (ISPASS, 2008)

CPR: Composable performance regression for scalable multiprocessor models. - Benjamin C. Lee; Jamison D. Collins; Hong Wang 003; David M. Brooks (MICRO, 2008)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

Intel nehalem processor core made FPGA synthesizable. - Graham Schelle; Jamison D. Collins; Ethan Schuchman; Perry H. Wang; Xiang Zou; Gautham N. Chinya; Ralf Plate; Thorsten Mattner; Franz Olbrich; Per Hammarlund; Ronak Singhal; Jim Brayton; et al. (FPGA, 2010)

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. - Guilherme Ottoni; Gautham N. Chinya; Gerolf Hoflehner; Jamison D. Collins; Amit Kumar; Ethan Schuchman; David R. Ditzel; Ronak Singhal; Hong Wang 003 (Conf. Computing Frontiers, 2011)

Bothnia: a dual-personality extension to the Intel integrated graphics driver. - Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Hong Jiang; Guei-Yuan Lueh; Thomas Piazza; Hong Wang 003 (ACM SIGOPS Oper. Syst. Rev., 2011)