Design and Evaluation of Arithmetic and Logic Unit Using Simulated Annealing. - Pavitra Y. J; Jamuna S; Manikandan J (ISCMI, 2023)

Design and Simulation of Fault Detection Technique for NAND Based Memory Array. - Jamuna S; Madhura R; Kishore Kumar K; Murali S. Bharadwaja (ATS, 2024)

Design and Simulation of Data Acquisition system using Ethernet for Zynq 7000 SoC FPGA. - Prajwal Angadi; S. Satwika; E. Shreya; Jamuna S (ECAI, 2024)