Laissez-Faire Caching for Parallel #SAT Solving. - Jan Burchard; Tobias Schubert 001; Bernd Becker 001 (SAT, 2015)

Distributed Parallel #SAT Solving. - Jan Burchard; Tobias Schubert 001; Bernd Becker 001 (CLUSTER, 2016)

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. - Jan Burchard; Dominik Erb; Adit D. Singh; Sudhakar M. Reddy; Bernd Becker 001 (DATE, 2017)

AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. - Jan Burchard; Mael Gay; Ange-Salomé Messeng Ekossono; Jan Horácek; Bernd Becker 001; Tobias Schubert 001; Martin Kreuzer; Ilia Polian (FDTC, 2017)

Towards mixed structural-functional models for algebraic fault attacks on ciphers. - Jan Burchard; Ange-Salomé Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker 001; Tobias Schubert 001; Martin Kreuzer; Ilia Polian (IVSW, 2017)

Evaluating the effectiveness of D-chains in SAT-based ATPG. - Jan Burchard; Felix Neubauer; Pascal Raiola; Dominik Erb; Bernd Becker 001 (LATS, 2017)

Integrating Algebraic and SAT Solvers. - Jan Horácek; Jan Burchard; Bernd Becker 001; Martin Kreuzer (MACIS, 2017)

Efficient SAT-based generation of hazard-activated TSOF tests. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (VTS, 2017)

Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG. - Pascal Raiola; Jan Burchard; Felix Neubauer; Dominik Erb; Bernd Becker 001 (J. Electron. Test., 2017)

Characterization of possibly detected faults by accurately computing their detection probability. - Jan Burchard; Dominik Erb; Bernd Becker 001 (DATE, 2018)

Efficient generation of parametric test conditions for AMS chips with an interval constraint solver. - Felix Neubauer; Jan Burchard; Pascal Raiola; Jochen Rivoir; Bernd Becker 001; Matthias Sauer 002 (VTS, 2018)

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. - Jan Burchard; Dominik Erb; Sudhakar M. Reddy; Adit D. Singh; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Applying advanced SAT-based techniques to circuit testing. - Jan Burchard (2018)

On Secure Data Flow in Reconfigurable Scan Networks. - Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (DATE, 2019)

High-Bandwidth IJTAG over SSN. - Jonathan Gaudet; Jan Burchard; Matthias Kampmann; Jean-François Côté; Tim Callahan; Hung Ho Chai; Ivy Ee Hsia Lim; Lori Schramm; Olga Przybysz; Marta Stepniewska; Sascha Ochsenknecht; Michal Olejarz; et al. (ITC, 2024)