Pipelined Dataflow Architecture of a Small Processor. - Juraj Povazanec; Oliver Chiu-sing Choy; Cheong-Fat Chan; Jan Butas; Yeu-qiu Zhang; Jing-Ling Yang; Tin-yan Tang (PDPTA, 1999)

An ALU design using a novel asynchronous pipeline architecture. - Tin-Yau Tang; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS, 2000)

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. - Chi-Wai Lee; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

A low power asynchronous DES. - Pui-Lam Siu; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

Asynchronous cross-pipelined multiplier. - Jan Butas; Chiu-Sing Choy; Juraj Povazanec; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A New Control Circuit for Asynchronous Micropipelines. - Oliver Chiu-sing Choy; Jan Butas; Juraj Povazanec; Cheong-Fat Chan (IEEE Trans. Computers, 2001)