A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors. - Ralf König 001; Timo Stripf; Jan Heisswolf; Jürgen Becker 001 (IPDPS Workshops, 2011)

Architecture design space exploration of run-time scalable issue-width processors. - Ralf König 001; Timo Stripf; Jan Heisswolf; Jürgen Becker 001 (ICSAMOS, 2011)

Hardware prototyping of novel invasive multicore architectures. - Jürgen Becker 001; Stephanie Friederich; Jan Heisswolf; Ralf König 001; David May 003 (ASP-DAC, 2012)

Invasive manycore architectures. - Jörg Henkel; Andreas Herkersdorf; Lars Bauer; Thomas Wild; Michael Hübner 001; Ravi Kumar Pujari; Artjom Grudnitsky; Jan Heisswolf; Aurang Zaib; Benjamin Vogel; Vahid Lari; Sebastian Kobbe (ASP-DAC, 2012)

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Ralf König 001; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (IPDPS Workshops, 2012)

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. - Jan Heisswolf; Ralf König 001; Jürgen Becker 001 (ISPA, 2012)

Hybrid interconnect design for heterogeneous hardware accelerators. - Cuong Pham-Quoc; Jan Heisswolf; Stephan Werner 002; Zaid Al-Ars; Jürgen Becker 001; Koen Bertels (DATE, 2013)

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. - Aurang Zaib; Jan Heisswolf; Andreas Weichslgartner; Thomas Wild; Jürgen Teich; Jürgen Becker 001; Andreas Herkersdorf (DSD, 2013)

Hardware Supported Adaptive Data Collection for Networks on Chip. - Jan Heisswolf; Andreas Weichslgartner; Aurang Zaib; Ralf König 001; Thomas Wild; Andreas Herkersdorf; Jürgen Teich; Jürgen Becker 001 (IPDPS Workshops, 2013)

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. - Jan Heisswolf; Maximilian Singh; Martin Kupper; Ralf König 001; Jürgen Becker 001 (ReConFig, 2013)

Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers. - Jan Heisswolf; Simon Bischof; Michael Rückauer; Jürgen Becker 001 (SBCCI, 2013)

NoC simulation in heterogeneous architectures for PGAS programming model. - Sascha Roloff; Andreas Weichslgartner; Jan Heißwolf; Frank Hannig; Jürgen Teich (M-SCOPES, 2013)

Providing multiple hard latency and throughput guarantees for packet switching networks on chip. - Jan Heisswolf; Ralf König 001; Martin Kupper; Jürgen Becker 001 (Comput. Electr. Eng., 2013)

Virtual networks - distributed communication resource management. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Ralf König 001; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Martin Karle; Maximilian Singh; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (ARCS Workshops, 2014)

CAP: Communication Aware Programming. - Jan Heisswolf; Aurang Zaib; Andreas Zwinkau; Sebastian Kobbe; Andreas Weichslgartner; Jürgen Teich; Jörg Henkel; Gregor Snelting; Andreas Herkersdorf; Jürgen Becker 001 (DAC, 2014)

Hardware/software debugging of large scale many-core architectures. - Stephanie Friederich; Jan Heisswolf; Jürgen Becker 001 (SBCCI, 2014)

A Scalable and Adaptive Network on Chip for Many-Core Architectures. - Jan Heißwolf (2014)

Fault-tolerant communication in invasive networks on chip. - Jan Heisswolf; Andreas Weichslgartner; Aurang Zaib; Stephanie Friederich; Leonard Masing; Carsten Stein; Marco Duden; Roman Klopfer; Jürgen Teich; Thomas Wild; Andreas Herkersdorf; Jürgen Becker 001 (AHS, 2015)

Network Interface with Task Spawning Support for NoC-Based DSM Architectures. - Aurang Zaib; Jan Heißwolf; Andreas Weichslgartner; Thomas Wild; Jürgen Teich; Jürgen Becker 001; Andreas Herkersdorf (ARCS, 2015)

A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. - Michael Dreschmann; Jan Heisswolf; Michael Geiger; Manuel Haußecker; Jürgen Becker 001 (SBCCI, 2015)

Providing fault tolerance through invasive computing. - Vahid Lari; Andreas Weichslgartner; Alexandru Tanase; Michael Witterauf; Faramarz Khosravi; Jürgen Teich; Jan Heißwolf; Stephanie Friederich; Jürgen Becker 001 (it Inf. Technol., 2016)

Efficient task spawning for shared memory and message passing in many-core architectures. - Aurang Zaib; Thomas Wild; Andreas Herkersdorf; Jan Heisswolf; Jürgen Becker 001; Andreas Weichslgartner; Jürgen Teich (J. Syst. Archit., 2017)