Essential Hazard Correction Without the Use of Delay Elements. - Jan Hlavicka (IEEE Trans. Computers, 1970)

Automatische Belegung von Flachbaugruppen im System PENTA-3. - Jan Hlavicka (Elektron. Rechenanlagen, 1973)

Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. - P. Golan; Ondrej Novák; Jan Hlavicka (IEEE Trans. Computers, 1988)

Validation and Verification of Hardware and Software (Position Statement). - Jan Hlavicka (IFIP Congress, 1989)

On the Complexity of System-Level Diagnosis Algorithms. - Jan Hlavicka (EUROCAST, 1991)

Position Paper. - Jan Hlavicka (EDCC, 1994)

Functional Validation of Fault-Tolerant Asynchronous Algorithms. - Jan Hlavicka; Stanislav Racek; Pavel Smrha (EUROMICRO, 1996)

Guest Editors' Introduction: East Meets West. - Yervant Zorian; Jan Hlavicka (IEEE Des. Test Comput., 1996)

RT Level Test Scheduling. - Jan Blatný; Zdenek Kotásek; Jan Hlavicka (Comput. Artif. Intell., 1997)

Formal Approach to the RTL Testability Analysis. - Zdenek Kotásek; Richard Ruzicka; Jan Hlavicka (LATW, 2000)

Evaluation of process controller fault tolerance using simulation. - Jan Hlavicka; Stanislav Racek; Pavel Herout (Simul. Pract. Theory, 2000)

On the Use of Mutations in Boolean Minimization. - Petr Fiser; Jan Hlavicka (DSD, 2001)

Minimization and Partitioning Method Reducing Input Sets. - Jan Hlavicka; Petr Fiser (DELTA, 2002)

C-Sim - The C Language Enhancement for Discrete-Time Simulations. - Jan Hlavicka; Stanislav Racek (DSN, 2002)

Model-Based Dependability Evaluation Method for TTP/C Based Systems. - Pavel Herout; Stanislav Racek; Jan Hlavicka (EDCC, 2002)

Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. - Astrit Ademaj; Petr Grillinger; Pavel Herout; Jan Hlavicka (IOLTW, 2002)

Fault-Tolerant FPGA-Based Systems. - Khaled Elshafey; Jan Hlavicka (Comput. Artif. Intell., 2002)

FC-Min: A Fast Multi-Output Boolean Minimizer. - Petr Fiser; Jan Hlavicka; Hana Kubátová (DSD, 2003)

BOOM - A Heuristic Boolean Minimizer. - Jan Hlavicka; Petr Fiser (Comput. Artif. Intell., 2003)

Dependability Evaluation of Time Triggered Architecture Using Simulation. - Stanislav Racek; Pavel Herout; Jan Hlavicka (Comput. Artif. Intell., 2004)