Software Pipelining for Transport-Triggered Architectures. - Jan Hoogerbrugge; Henk Corporaal; Hans M. Mulder (MICRO, 1991)

Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture. - Jan Hoogerbrugge; Henk Corporaal (CC, 1992)

Transport-Triggering versus Operation-Triggering. - Jan Hoogerbrugge; Henk Corporaal (CC, 1994)

Code generation for transport triggered architectures. - Henk Corporaal; Jan Hoogerbrugge (Code Generation for Embedded Processors, 1994)

Register file port requirements of transport triggered architectures. - Jan Hoogerbrugge; Henk Corporaal (MICRO, 1994)

OCEANS: Optimizing Compilers for Embedded Applications. - Bas Aarts; Michel Barreteau; François Bodin; Peter Brinkhaus; Zbigniew Chamski; Henri-Pierre Charles; Christine Eisenbeis; John R. Gurd; Jan Hoogerbrugge; Ping Hu; William Jalby; Peter M. W. Knijnenburg; et al. (Euro-Par, 1997)

OCEANS: Optimising Compilers for Embedded Applications. - Michel Barreteau; François Bodin; Peter Brinkhaus; Zbigniew Chamski; Henri-Pierre Charles; Christine Eisenbeis; John R. Gurd; Jan Hoogerbrugge; Ping Hu; William Jalby; Peter M. W. Knijnenburg; Michael F. P. O'Boyle; et al. (Euro-Par, 1998)

OCEANS - Optimising Compilers for Embedded Applications. - Michel Barreteau; François Bodin; Zbigniew Chamski; Henri-Pierre Charles; Christine Eisenbeis; John R. Gurd; Jan Hoogerbrugge; Ping Hu; William Jalby; Toru Kisuki; Peter M. W. Knijnenburg; Paul van der Mark; et al. (Euro-Par, 1999)

ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. - Bernardo Kastrup; Arjan Bink; Jan Hoogerbrugge (FCCM, 1999)

Instruction Scheduling for TriMedia. - Jan Hoogerbrugge; Lex Augusteijn (J. Instr. Level Parallelism, 1999)

A Code Compression System Based on Pipelined Interpreters. - Jan Hoogerbrugge; Lex Augusteijn; Jeroen Trum; Rik van de Wiel (Softw. Pract. Exp., 1999)

Dynamic Branch Prediction for a VLIW Processor. - Jan Hoogerbrugge (IEEE PACT, 2000)

Pipelined Java Virtual Machine Interpreters. - Jan Hoogerbrugge; Lex Augusteijn (CC, 2000)

Cost-Efficient Branch Target Buffers. - Jan Hoogerbrugge (Euro-Par, 2000)

Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. - Bernardo Kastrup; Jeroen Trum; Orlando Moreira; Jan Hoogerbrugge; Jef L. van Meerbergen (FPL, 2000)

Exploring design space of parallel realizations: MPEG-2 decoder case study. - Basant Kumar Dwivedi; Jan Hoogerbrugge; Paul Stravers; M. Balakrishnan (CODES, 2001)

Parallel H.264 Decoding on an Embedded Multicore Processor. - Arnaldo Azevedo; Cor Meenderinck; Ben H. H. Juurlink; Andrei Sergeevich Terechko; Jan Hoogerbrugge; Mauricio Alvarez 001; Alex Ramírez (HiPEAC, 2009)

A Highly Scalable Parallel Implementation of H.264. - Arnaldo Azevedo; Ben H. H. Juurlink; Cor Meenderinck; Andrei Sergeevich Terechko; Jan Hoogerbrugge; Mauricio Alvarez 001; Alex Ramírez; Mateo Valero (Trans. High Perform. Embed. Archit. Compil., 2011)

A Multithreaded Multicore System for Embedded Media Processing. - Jan Hoogerbrugge; Andrei Sergeevich Terechko (Trans. High Perform. Embed. Archit. Compil., 2011)

Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures. - Andrei Sergeevich Terechko; Jan Hoogerbrugge; Ghiath Alkadi; Surendra Guntur; Anirban Lahiri; Marc Duranton; Clemens C. Wüst; Phillip Christie; Axel Nackaerts; Aatish Kumar (ACM Trans. Embed. Comput. Syst., 2012)

Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation. - Surendra Guntur; Feike Jansen; Jan Hoogerbrugge; Lotfi Abkari; Eric Vos (FPL, 2013)

Variation tolerance and error resilience in a low power wireless receiver. - Jan Hoogerbrugge (ICCD, 2013)

CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory. - Pascal Nasahl; Robert Schilling; Mario Werner; Jan Hoogerbrugge; Marcel Medwed; Stefan Mangard (AsiaCCS, 2021)