An In-DRAM Neural Network Processing Engine. - Chirag Sudarshan; Jan Lappas; Muhammad Mohsin Ghaffar; Vladimir Rybalkin; Christian Weis; Matthias Jung 001; Norbert Wehn (ISCAS, 2019)

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. - Chirag Sudarshan; Jan Lappas; Christian Weis; Deepak M. Mathew; Matthias Jung 001; Norbert Wehn (SAMOS, 2019)

Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2020)

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. - Chirag Sudarshan; Lukas Steiner; Matthias Jung 001; Jan Lappas; Christian Weis; Norbert Wehn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2021)

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node. - Jan Lappas; André Lucas Chinazzo; Christian Weis; Chenyang Xia; Zhihang Wu; Leibin Ni; Norbert Wehn (DATE, 2022)

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication. - Zhe Zhang; Jan Lappas; André Lucas Chinazzo; Christian Weis; Zhihang Wu; Leibin Ni; Norbert Wehn; Mehdi B. Tahoori (ETS, 2022)

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology. - André Lucas Chinazzo; Jan Lappas; Christian Weis; Qinhui Huang; Zhihang Wu; Leibin Ni; Norbert Wehn (ICECS 2022, 2022)

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. - Chirag Sudarshan; Taha Soliman; Jan Lappas; Christian Weis; Mohammad Hassani Sadi; Matthias Jung 001; Andre Guntoro; Norbert Wehn (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Timing Analysis beyond Complementary CMOS Logic Styles. - Jan Lappas; Mohamed Amine Riahi; Christian Weis; Norbert Wehn; Sani R. Nassif (ASPDAC, 2024)

Timing Analysis with Analytical Sensitivity. - Jan Lappas; Norbert Wehn; Sani R. Nassif (ISOCC, 2024)

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces. - Mohammadreza Esmaeilpour; Jan Lappas; Hussien Abdo; Christian Weis; Norbert Wehn (NewCAS, 2024)

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces. - Mohammadreza Esmaeilpour; Jan Lappas; Christian Weis; Norbert Wehn (NorCAS, 2024)

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology. - Mohammadreza Esmaeilpour; Jan Lappas; Christian Weis; Norbert Wehn (VLSI-SoC, 2024)

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables. - Hussien Abdo; Jan Lappas; Mohammadreza Esmaeilpour; Christian Weis; Norbert Wehn (DDECS, 2025)

A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique. - Mohammadreza Esmaeilpour; Marco Mestice; Jan Lappas; Christian Weis; Norbert Wehn (NewCAS, 2025)

Enhanced LPDDR4X PHY in 12 nm FinFET. - Johannes Feldmann; Jan Lappas; Mohammadreza Esmaeilpour; Hussien Abdo; Christian Weis; Norbert Wehn (CoRR, 2025)