A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. - Jan Moritz Joseph; Thilo Pionteck (ISSoC, 2014)

A model for dynamical evolution of science in space. - Jan Moritz Joseph; Jens Christian Claussen (CoRR, 2014)

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. - Jan Moritz Joseph; Christopher Blochwitz; Thilo Pionteck; Alberto García Ortiz (NORCAS, 2015)

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. - Christopher Blochwitz; Jan Moritz Joseph; Rico Backasch; Thilo Pionteck; Stefan Werner 002; Dennis Heinrich; Sven Groppe (ReConFig, 2015)

Adaptive allocation of default router paths in Network-on-Chips for latency reduction. - Jan Moritz Joseph; Christopher Blochwitz; Thilo Pionteck (HPCS, 2016)

Hardware-accelerated pose estimation for embedded systems using Vivado HLS. - Jan Moritz Joseph; Tobias Winker; Kristian Ehlers; Christopher Blochwitz; Thilo Pionteck (ReConFig, 2016)

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. - Jan Moritz Joseph; Sven Wrieden; Christopher Blochwitz; Alberto García Ortiz; Thilo Pionteck (ReCoSoC, 2016)

Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. - Christopher Blochwitz; Julian Wolff; Jan Moritz Joseph; Stefan Werner 002; Dennis Heinrich; Sven Groppe; Thilo Pionteck (ARCS, 2017)

Continuous live-tracing as debugging approach on FPGAs. - Christopher Blochwitz; Raphael Klink; Jan Moritz Joseph; Thilo Pionteck (ReConFig, 2017)

An FPGA-based prototyping framework for Networks-on-Chip. - Tobias Drewes; Jan Moritz Joseph; Thilo Pionteck (ReConFig, 2017)

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. - Jan Moritz Joseph; Morten Mey; Kristian Ehlers; Christopher Blochwitz; Tobias Winker; Thilo Pionteck (ReConFig, 2017)

Design method for asymmetric 3D interconnect architectures with high level models. - Jan Moritz Joseph; Lennart Bamberg; Sven Wrieden; Dominik Ermel; Alberto García Ortiz; Thilo Pionteck (ReCoSoC, 2017)

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. - Jan Moritz Joseph; Christopher Blochwitz; Alberto García Ortiz; Thilo Pionteck (Microprocess. Microsystems, 2017)

Hardware-Accelerated Index Construction for Semantic Web. - Christopher Blochwitz; Julian Wolff; Mladen Berekovic; Dennis Heinrich; Sven Groppe; Jan Moritz Joseph; Thilo Pionteck (FPT, 2018)

Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. - Tobias Drewes; Jan Moritz Joseph; Bala Gurumurthy; David Broneske; Gunter Saake; Thilo Pionteck (FPT, 2018)

Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. - Lennart Bamberg; Jan Moritz Joseph; Robert Schmidt 003; Thilo Pionteck; Alberto García Ortiz (PATMOS, 2018)

Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. - Jan Moritz Joseph; Lennart Bamberg; Gerald Krell; Imad Hajjar; Alberto García Ortiz; Thilo Pionteck (ReCoSoC, 2018)

System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. - Jan Moritz Joseph; Dominik Ermel; Lennart Bamberg; Alberto García Ortiz; Thilo Pionteck (ICCD, 2019)

Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. - Daniele Passaretti; Jan Moritz Joseph; Thilo Pionteck (FPT, 2019)

Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. - Jan Moritz Joseph; Dominik Ermel; Tobias Drewes; Lennart Bamberg; Alberto García-Ortiz; Thilo Pionteck (MOCAST, 2019)

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. - Jan Moritz Joseph; Lennart Bamberg; Dominik Ermel; Behnam Razi Perjikolaei; Anna Drewes; Alberto García Ortiz; Thilo Pionteck (IEEE Access, 2019)

Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Behnam Razi Perjikolaei; Alberto García Ortiz; Thilo Pionteck (CoRR, 2019)

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. - Lennart Bamberg; Jan Moritz Joseph; Thilo Pionteck; Alberto García Ortiz (Integr., 2019)

Simulation environment for link energy estimation in networks-on-chip with virtual channels. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Robert Schmidt 003; Thilo Pionteck; Alberto García Ortiz (Integr., 2019)

Optimising Operator Sets for Analytical Database Processing on FPGAs. - Anna Drewes; Jan Moritz Joseph; Bala Gurumurthy; David Broneske; Gunter Saake; Thilo Pionteck (ARC, 2020)

A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim. - Ananda Samajdar; Jan Moritz Joseph; Yuhao Zhu 001; Paul N. Whatmough; Matthew Mattina; Tushar Krishna (ISPASS, 2020)

Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. - Jan Moritz Joseph; Lennart Bamberg; Geonhwa Jeong; Ruei-Ting Chien; Rainer Leupers; Alberto García-Ortiz; Tushar Krishna; Thilo Pionteck (ASP-DAC, 2021)

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. - Jan Moritz Joseph; Ananda Samajdar; Lingjun Zhu; Rainer Leupers; Sung Kyu Lim; Thilo Pionteck; Tushar Krishna (ISQED, 2021)

Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies. - Lennart Bamberg; Tushar Krishna; Jan Moritz Joseph (NANOCOM, 2021)

NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. - Jan Moritz Joseph; Murat Sezgin Baloglu; Yue Pan; Rainer Leupers; Lennart Bamberg (NOCS, 2021)

AIRCHITECT: Learning Custom Architecture Design and Mapping Space. - Ananda Samajdar; Jan Moritz Joseph; Matthew Denton; Tushar Krishna (CoRR, 2021)

X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. - Felix Staudigl; Karl J. X. Sturm; Maximilian Bartel; Thorben Fetz; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Bolzani Pöhls; Rainer Leupers (AICAS, 2022)

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. - Felix Staudigl; Hazem Al Indari; Daniel Schön; Dominik Sisejkovic; Farhad Merchant; Jan Moritz Joseph; Vikas Rana; Stephan Menzel; Rainer Leupers (DATE, 2022)

EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. - Yee Yang Tan; Felix Staudigl; Lukas Jünger 001; Anna Drewes; Rainer Leupers; Jan Moritz Joseph (FPL, 2022)

NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. - Nils Bosbach; Jan Moritz Joseph; Rainer Leupers; Lukas Jünger 001 (VLSI-SoC, 2022)

Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. - Jan Moritz Joseph; Lennart Bamberg; Imad Hajjar; Behnam Razi Perjikolaei; Alberto García-Ortiz; Thilo Pionteck (ACM Trans. Model. Comput. Simul., 2022)

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. - Felix Staudigl; Mohammed Hossein; Tobias Ziegler 005; Hazem Al Indari; Rebecca Pelke; Sebastian Siegel; Dirk J. Wouters; Dominik Sisejkovic; Jan Moritz Joseph; Rainer Leupers (CODES+ISSS, 2023)

Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. - Felix Staudigl; Thorben Fetz; Rebecca Pelke; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Bolzani Pöhls; Rainer Leupers (DAC, 2023)

AIrchitect: Automating Hardware Architecture and Mapping Optimization. - Ananda Samajdar; Jan Moritz Joseph; Tushar Krishna (DATE, 2023)

par-gem5: Parallelizing gem5's Atomic Mode. - Niko Zurstraßen; José Cubero-Cascante; Jan Moritz Joseph; Li Yichao; Xinghua Xie; Rainer Leupers (DATE, 2023)

Efficient RISC-V-on-x64 Floating Point Simulation. - Niko Zurstraßen; Nils Bosbach; Jan Moritz Joseph; Lukas Jünger 001; Jan Henrik Weinstock; Rainer Leupers (ICCD, 2023)

Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. - Felix Staudigl; Thorben Fetz; Rebecca Pelke; Dominik Sisejkovic; Jan Moritz Joseph; Letícia Maria Veiras Bolzani Poehls; Rainer Leupers (LATS, 2023)

parti-gem5: gem5's Timing Mode Parallelised. - José Cubero-Cascante; Niko Zurstraßen; Jörn Nöller; Rainer Leupers; Jan Moritz Joseph (SAMOS, 2023)

Mapping of CNNs on multi-core RRAM-based CIM architectures. - Rebecca Pelke; Nils Bosbach; José Cubero-Cascante; Felix Staudigl; Rainer Leupers; Jan Moritz Joseph (VLSI-SoC, 2023)

Architecture-Compiler Co-design for ReRAM-Based Multi-core CIM Architectures. - Rebecca Pelke; Nils Bosbach; Niklas Degener; José Cubero-Cascante; Felix Staudigl; Rainer Leupers; Jan Moritz Joseph (VLSI-SoC (Selected Papers), 2023)

A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars. - José Cubero-Cascante; Arunkumar Vaidyanathan; Rebecca Pelke; Lorenzo Pfeifer; Rainer Leupers; Jan Moritz Joseph (AICAS, 2024)

NVM-Flip: Non-Volatile-Memory BitFlips on the System Level. - Felix Staudigl; Jan Philipp Thoma; Christian Niesler; Karl J. X. Sturm; Rebecca Pelke; Dominik Germek; Jan Moritz Joseph; Tim Güneysu; Lucas Davi; Rainer Leupers (SAT-CPS@CODASPY, 2024)

CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. - Rebecca Pelke; José Cubero-Cascante; Nils Bosbach; Felix Staudigl; Rainer Leupers; Jan Moritz Joseph (DATE, 2024)

A Fully Automated Platform for Evaluating ReRAM Crossbars. - Rebecca Pelke; Felix Staudigl; Niklas Thomas; Nils Bosbach; Mohammed Hossein; José Cubero-Cascante; Letícia Maria Veiras Bolzani; Rainer Leupers; Jan Moritz Joseph (LATS, 2024)

Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators. - Lorenzo Pfeifer; M. Gross; Felix Staudigl; Rainer Leupers; Jan Moritz Joseph (LATS, 2024)

Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer. - Rebecca Pelke; José Cubero-Cascante; Nils Bosbach; Niklas Degener; Florian Idrizi; Lennart M. Reimann; Jan Moritz Joseph; Rainer Leupers (CoRR, 2025)