A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (A-SSCC, 2014)

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)

Adaptive high-speed and ultra-low power optical interconnect for data center communications. - Ronny Henker; Thomas Toifl; Alessandro Cevrero; Ilter Oezkaya; Michael Georgiades; Mahdi M. Khafaji; Jan Plíva; Frank Ellinger (ICTON, 2017)

Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS. - Jan Plíva; Mahdi M. Khafaji; László Szilágyi; Ronny Henker; Frank Ellinger (SoCC, 2017)

4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS. - Alessandro Cevrero; Ilter Özkaya; Thomas Morf; Thomas Toifl; M. Seifried; Frank Ellinger; Mohammad Mahdi Khafaji; Jan Plíva; Ronny Henker; Nikolay N. Ledentsov; J.-R. Kropp; V. A. Shchukin; et al. (OFC, 2018)

A 4×45 Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation. - Mohammad Mahdi Khafaji; Guido Belfiore; Jan Plíva; Ronny Henker; Frank Ellinger (IEEE J. Solid State Circuits, 2018)

Combinational Decompressors with Nonlinear Codes. - Ondrej Novák; Martin Rozkovec; Jan Plíva (DSD, 2019)

A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment. - Tobias Schirmer; Mohammad Mahdi Khafaji; Jan Plíva; Frank Ellinger (SoCC, 2019)

Offset-Compensation Systems for Multi-Gbit/s Optical Receivers. - László Szilágyi; Jan Plíva; Ronny Henker (VLSI-SoC (Selected Papers), 2019)

A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends. - László Szilágyi; Jan Plíva; Ronny Henker; Frank Ellinger (VLSI-SoC, 2019)

A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS. - László Szilágyi; Jan Plíva; Ronny Henker; David Schoeniger; Jaroslaw P. Turkiewicz; Frank Ellinger (IEEE J. Solid State Circuits, 2019)

A Low-Power Fast Settling 5.4 - 8.4 GHz Digitally Controlled Oscillator in 45 nm RFSOI CMOS. - Rui Ma; Florian Protze; Jan Plíva; Martin Kreißig; Frank Ellinger (MWSCAS, 2020)

Decompressors using nonlinear codes. - Ondrej Novák; Martin Rozkovec; Jan Plíva (Microprocess. Microsystems, 2020)