A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. - Jan Mulder; Christopher M. Ward; Chi-Hung Lin; David Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; Rudy J. van de Plassche; Klaas Bult; Frank M. L. van der Goes (IEEE J. Solid State Circuits, 2004)

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. - Chi-Hung Lin; Frank M. L. van der Goes; Jan R. Westra; Jan Mulder; Yu Lin; Erol Arslan; Emre Ayranci; Xiaodong Liu; Klaas Bult (ISSCC, 2009)

A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. - Chi-Hung Lin; Frank M. L. van der Goes; Jan R. Westra; Jan Mulder; Yu Lin; Erol Arslan; Emre Ayranci; Xiaodong Liu; Klaas Bult (IEEE J. Solid State Circuits, 2009)

An 800MS/s dual-residue pipeline ADC in 40nm CMOS. - Jan Mulder; Frank M. L. van der Goes; Davide Vecchi; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (ISSCC, 2011)

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. - Davide Vecchi; Jan Mulder; Frank M. L. van der Goes; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (IEEE J. Solid State Circuits, 2011)

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (CICC, 2014)

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (ISSCC, 2014)

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. - Jan Mulder; Davide Vecchi; Yi Ke; Stefano Bozzola; Mark Core; Nitz Saputra; Qiongna Zhang; Jeff Riley; Han Yan; Mattia Introini; Sijia Wang; Christopher M. Ward; et al. (ISSCC, 2015)