Jan Reineke

Orcid: 0000-0002-3459-2214

Affiliations:
  • Saarland University, Department of Computer Science


According to our database1, Jan Reineke authored at least 85 papers between 2006 and 2024.

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Bibliography

2024
Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors.
CoRR, 2024

2023
Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms.
IEEE Trans. Computers, May, 2023

Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis.
Proceedings of the IEEE Real-Time Systems Symposium, 2023

Facile: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

2022
LLVMTA: An LLVM-Based WCET Analysis Tool.
Proceedings of the 20th International Workshop on Worst-Case Execution Time Analysis, 2022

On the Trade-offs between Generalization and Specialization in Real-Time Systems.
Proceedings of the 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2022

Warping cache simulation of polyhedral programs.
Proceedings of the PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13, 2022

uiCA: accurate throughput prediction of basic blocks on recent intel microarchitectures.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2021
Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures.
CoRR, 2021

Hardware-Software Contracts for Secure Speculation.
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021

2020
Design and analysis of SIC: a provably timing-predictable pipelined processor core.
Real Time Syst., 2020

Flushgeist: Cache Leaks from Beyond the Flush.
CoRR, 2020

Spectector: Principled Detection of Speculative Information Flows.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019
Basic problems in multi-view modeling.
Softw. Syst. Model., 2019

Fast and exact analysis for LRU caches.
Proc. ACM Program. Lang., 2019

On the Incomparability of Cache Algorithms in Terms of Timing Leakage.
Log. Methods Comput. Sci., 2019

Cache Persistence Analysis: Finally Exact.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Checking multi-view consistency of discrete systems with respect to periodic sampling abstractions.
Sci. Comput. Program., 2018

Response-time analysis for fixed-priority systems with a write-back cache.
Real Time Syst., 2018

An extensible framework for multicore response time analysis.
Real Time Syst., 2018

On the Smoothness of Paging Algorithms.
Theory Comput. Syst., 2018

The Semantic Foundations and a Landscape of Cache-Persistence Analyses.
Leibniz Trans. Embed. Syst., 2018

Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis.
Proceedings of the 18th International Workshop on Worst-Case Execution Time Analysis, 2018

Keeping up with Real Time.
Proceedings of the Advances in Aeronautical Informatics, Technologies Towards Flight 4.0., 2018

2017
Abstract PRET Machines.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Memory Bank Partitioning for Fixed-Priority Tasks in a Multi-core System.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Security Analysis of Cache Replacement Policies.
Proceedings of the Principles of Security and Trust - 6th International Conference, 2017

Write-Back Caches in WCET Analysis.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Ascertaining Uncertainty for Efficient Exact Cache Analysis.
Proceedings of the Computer Aided Verification - 29th International Conference, 2017

2016
A Survey on Static Cache Analysis for Real-Time Systems.
Leibniz Trans. Embed. Syst., 2016

Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Enabling Compositionality for Multicore Timing Analysis.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Gray-Box Learning of Serial Compositions of Mealy Machines.
Proceedings of the NASA Formal Methods - 8th International Symposium, 2016

MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Static Timing Analysis - What is Special?
Proceedings of the Semantics, Logics, and Calculi, 2016

2015
CacheAudit: A Tool for the Static Analysis of Cache Side Channels.
ACM Trans. Inf. Syst. Secur., 2015

Towards compositionality in execution time analysis: definition and challenges.
SIGBED Rev., 2015

WCET and Mixed-Criticality: What does Confidence in WCET Estimations Depend Upon?.
Proceedings of the 15th International Workshop on Worst-Case Execution Time Analysis, 2015

Analysis of Infinite-State Graph Transformation Systems by Cluster Abstraction.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

ASTRA: A Tool for Abstract Interpretation of Graph Transformation Systems.
Proceedings of the Model Checking Software - 22nd International Symposium, 2015

A generic and compositional framework for multicore response time analysis.
Proceedings of the 23rd International Conference on Real Time Networks and Systems, 2015

MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Toward Compact Abstractions for Processor Pipelines.
Proceedings of the Correct System Design, 2015

2014
Building timing predictable embedded systems.
ACM Trans. Embed. Comput. Syst., 2014

Randomized Caches Considered Harmful in Hard Real-Time Systems.
Leibniz Trans. Embed. Syst., 2014

Basic Problems in Multi-View Modeling.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2014

A Compiler Optimization to Increase the Efficiency of WCET Analysis.
Proceedings of the 22nd International Conference on Real-Time Networks and Systems, 2014

Architecture-parametric timing analysis.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Selfish-LRU: Preemption-aware caching for predictability and performance.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Reverse engineering of cache replacement policies in Intel microprocessors and their evaluation.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Impact of resource sharing on performance and performance prediction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Sensitivity of cache replacement policies.
ACM Trans. Embed. Comput. Syst., 2013

CacheAudit: A Tool for the Static Analysis of Cache Side Channels.
IACR Cryptol. ePrint Arch., 2013

Measurement-based modeling of the cache replacement policy.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Precise timing analysis for direct-mapped caches.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Impact of Resource Sharing on Performance and Performance Prediction: A Survey.
Proceedings of the CONCUR 2013 - Concurrency Theory - 24th International Conference, 2013

2012
An Empirical Evaluation of the Influence of the Load-Store Unit on WCET Analysis.
Proceedings of the 12th International Workshop on Worst-Case Execution Time Analysis, 2012

Embedded systems: Many cores - Many problems.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

A PRET microarchitecture implementation with repeatable timing and competitive performance.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Branch target buffers: WCET analysis framework and timing predictability.
J. Syst. Archit., 2011

CAMA: A Predictable Cache-Aware Memory Allocator.
Proceedings of the 23rd Euromicro Conference on Real-Time Systems, 2011

A Template for Predictability Definitions with Supporting Evidence.
Proceedings of the Bringing Theory to Practice: Predictability and Performance in Embedded Systems, 2011

Temporal isolation on multiprocessing architectures.
Proceedings of the 48th Design Automation Conference, 2011

Designing next-generation real-time streaming systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

PRET DRAM controller: bank privatization for predictability and temporal isolation.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Toward Precise PLRU Cache Analysis.
Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis, 2010

Static Timing Analysis for Hard Real-Time Systems.
Proceedings of the Verification, 2010

Resilience analysis: tightening the CRPD bound for set-associative caches.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Precise and Efficient FIFO-Replacement Analysis Based on Static Phase Detection.
Proceedings of the 22nd Euromicro Conference on Real-Time Systems, 2010

2009
Caches in WCET Analysis: Predictability - Competitiveness - Sensitivity.
PhD thesis, 2009

Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Sound and Efficient WCET Analysis in the Presence of Timing Anomalies.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Making Dynamic Memory Allocation Static to Support WCET Analysis.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Cache-Related Preemption Delay Computation for Set-Associative Caches - Pitfalls and Solutions.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Abstract Interpretation of FIFO Replacement.
Proceedings of the Static Analysis, 16th International Symposium, 2009

Polynomial Precise Interval Analysis Revisited.
Proceedings of the Efficient Algorithms, 2009

2008
Relative competitiveness of cache replacement policies.
Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

Estimating the Performance of Cache Replacement Policies.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Relative competitive analysis of cache replacement policies.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

2007
Timing predictability of cache replacement policies.
Real Time Syst., 2007

2006
A Definition and Classification of Timing Anomalies.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

Shape Analysis of Sets.
Proceedings of the Workshop "Trustworthy Software" 2006, 2006


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