Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. - Jan Schat (ICECS, 2006)

Testing low-resolution DACs using the Generalized Morse Sequence as Stimulus Sequence for Cancelling DC drift. - Jan Schat (ICECS, 2007)

Fault Clustering in deep-submicron CMOS Processes. - Jan Schat (DATE, 2008)

Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. - Jan Schat (DDECS, 2008)

Evaluation of the Iddq Signature in devices with Gauss-distributed background current. - Jan Schat (DDECS, 2008)

On the relationship between stuck-at fault coverage and transition fault coverage. - Jan Schat (DATE, 2009)

Core-Based Testing of Embedded Mixed-Signal Modules in a SoC. - Vladimir A. Zivkovic; Jan Schat; Frank van der Heyden; Geert Seuren (IEEE Des. Test Comput., 2009)

Soft-error detection in Register Files using circular scan. - Jan Schat (DTIS, 2017)

ISO26262-compliant soft-error mitigation in register banks. - Jan Schat (ETS, 2017)

On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter. - Jan Schat (DATE, 2018)

ADC test methods using an impure stimulus: A survey. - Jan Schat (ETS, 2018)

Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter. - Jan Schat; Ulrich Möhlmann (ETS, 2019)