A 80 Mb/s low-power scalable turbo codec core. - Alexandre Giulietti; Bruno Bougard; Veerle Derudder; Steven Dupont; Jan-Willem Weijers; Liesbet Van der Perre (CICC, 2002)

A performance and complexity comparison of auto-correlation and cross-correlation for OFDM burst synchronization. - Andrew Fort; Jan-Willem Weijers; Veerle Derudder; Wolfgang Eberle; André Bourdoux (ICASSP (2), 2003)

From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow. - Jan-Willem Weijers; Veerle Derudder; Sven Janssens; Frederik Petré; André Bourdoux (EURASIP J. Adv. Signal Process., 2006)

ESL design and HW/SW co-verification of high-end software defined radio platforms. - A. C. H. Ng; Jan-Willem Weijers; Miguel Glassee; Thomas Schuster; Bruno Bougard; Liesbet Van der Perre (CODES+ISSS, 2007)

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. - Meng Li 012; Jan-Willem Weijers; Veerle Derudder; Ilse Vos; Maxim Rykunov; Steven Dupont; Peter Debacker; Andy Dewilde; Yanxiang Huang; Liesbet Van der Perre; Wim Van Thillo (A-SSCC, 2015)

A 16384-electrode 1024-channel multimodal CMOS MEA for high-throughput intracellular action potential measurements and impedance spectroscopy in drug-screening applications. - Carolina Mora Lopez; Ho Sung Chun; Laurent Berti; Shiwei Wang 001; Jan Putzeys; Carl Van Den Bulcke; Jan-Willem Weijers; Andrea Firrincieli; Veerle Reumers; Dries Braeken; Nick Van Helleputte (ISSCC, 2018)

A Multimodal CMOS MEA for High-Throughput Intracellular Action Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications. - Carolina Mora Lopez; Ho Sung Chun; Shiwei Wang 001; Laurent Berti; Jan Putzeys; Carl Van Den Bulcke; Jan-Willem Weijers; Andrea Firrincieli; Veerle Reumers; Dries Braeken; Nick Van Helleputte (IEEE J. Solid State Circuits, 2018)

A 77-dB DR 16-Ch 2nd-order Δ-ΔΣ Neural Recording Chip with 0.0077mm2/Ch. - Shiwei Wang 001; Marco Ballini; Xiaolin Yang; Chutham Sawigun; Jan-Willem Weijers; Dwaipayan Biswas; Carolina Mora Lopez (VLSI Circuits, 2021)

A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition. - Xiaolin Yang; Marco Ballini; Chutham Sawigun; Wen-Yang Hsu; Jan-Willem Weijers; Jan Putzeys; Carolina Mora Lopez (VLSI Technology and Circuits, 2022)

An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition. - Xiaolin Yang; Marco Ballini; Chutham Sawigun; Wen-Yang Hsu; Jan-Willem Weijers; Jan Putzeys; Carolina Mora Lopez (IEEE J. Solid State Circuits, 2023)