Improving the Throughput of a Pipeline by Insertion of Delays. - Janak H. Patel; Edward S. Davidson (ISCA, 1976)

Pipelines wth Internal Buffers. - Janak H. Patel (ISCA, 1978)

Processor-Memory Interconnections for Multiprocessors. - Janak H. Patel (ISCA, 1979)

PM4 - A reconfigurable multiprocessor system for pattern recognition and image processing. - Faye A. Briggs; King-Sun Fu; Kai Hwang 001; Janak H. Patel (MARK, 1979)

An Alternative to the Distributed Pipeline. - Janak H. Patel (IEEE Trans. Computers, 1980)

Performance of Processor-Memory Interconnections for Multiprocessors. - Janak H. Patel (IEEE Trans. Computers, 1981)

A performance model for instruction prefetch in pipelined instruction units. - Gregory F. Grohoski; Janak H. Patel (ICPP, 1982)

Analysis of Multiprocessors with Private Cache Memories. - Janak H. Patel (IEEE Trans. Computers, 1982)

Concurrent Error Detection in ALU's by Recomputing with Shifted Operands. - Janak H. Patel; Leona Y. Fung (IEEE Trans. Computers, 1982)

Memory Interference in Synchronous Multiprocessor Systems. - David W. L. Yen; Janak H. Patel; Edward S. Davidson (IEEE Trans. Computers, 1982)

Performance of Shared Cache for Parallel-Pipelined Computer Systems - Phil C. C. Yeh; Janak H. Patel; Edward S. Davidson (ISCA, 1983)

Concurrent Error Detection in Multiply and Divide Arrays. - Janak H. Patel; Leona Y. Fung (IEEE Trans. Computers, 1983)

Shared Cache for Multiple-Stream Computer Systems. - Phil C. C. Yeh; Janak H. Patel; Edward S. Davidson (IEEE Trans. Computers, 1983)

A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. - Mark S. Papamarcos; Janak H. Patel (ISCA, 1984)

Design of Test Pattern Generators for Built-In Test. - Ramaswami Dandapani; Janak H. Patel; Jacob A. Abraham (ITC, 1984)

Parallel Garbage Collection Without Synchronization Overhead. - Ashwin Ram 001; Janak H. Patel (ISCA, 1985)

An Efficient LISP-Execution Architecture with a New Representation for List Structures. - Gurindar S. Sohi; Edward S. Davidson; Janak H. Patel (ISCA, 1985)

Multiple-Fault Detection in Iterative Logic Arrays. - Wu-Tung Cheng; Janak H. Patel (ITC, 1985)

Compiler Directed Memory Management Policy For Numerical Programs. - Mohammad Malkawi; Janak H. Patel (SOSP, 1985)

Effectiveness of heuristics measures for automatic test pattern generation. - Sanjay J. Patel; Janak H. Patel (DAC, 1986)

Performance Measurement of Paging Behavior in Multiprogramming Systems. - Mohammad Malkawi; Janak H. Patel (ISCA, 1986)

A Hierarchical Approach Test Vector Generation. - Susheel J. Chandra; Janak H. Patel (DAC, 1987)

Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. - Pinaki Mazumder; Janak H. Patel; W. Kent Fuchs (DAC, 1987)

Parallel Garbage Collection on a Virtual Memory System. - Santosh G. Abraham; Janak H. Patel (ICPP, 1987)

Performance Evaluation of Multiple Register Sets. - Richard J. Eickemeyer; Janak H. Patel (ISCA, 1987)

A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. - Wu-Tung Cheng; Janak H. Patel (IEEE Trans. Computers, 1987)

Compaction of ATPG-generated test sequences for sequential circuits. - Rabindra K. Roy; Thomas M. Niermann; Janak H. Patel; Jacob A. Abraham; Resve A. Saleh (ICCAD, 1988)

Test generation in a parallel processing environment. - Susheel J. Chandra; Janak H. Patel (ICCD, 1988)

A Parallel Processing Architecture for an Integrated Vision System. - Alok N. Choudhary; Janak H. Patel (ICPP (1), 1988)

Performance Evaluation of On-Chip Register and Cache Organizations. - Richard J. Eickemeyer; Janak H. Patel (ISCA, 1988)

Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. - Subhasis Laha; Janak H. Patel; Ravishankar K. Iyer (IEEE Trans. Computers, 1988)

Methodologies for testing embedded content addressable memories. - Pinaki Mazumder; Janak H. Patel; W. Kent Fuchs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A Functional-Level Test Generation Methodology Using Two-level Representations. - Utpal J. Davé; Janak H. Patel (DAC, 1989)

Accurate logic simulation in the presence of unknowns. - Susheel J. Chandra; Janak H. Patel (ICCAD, 1989)

The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm. - Jeff Baxter; Janak H. Patel (ICPP (2), 1989)

Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. - Kun-Lung Wu; W. Kent Fuchs; Janak H. Patel (ICPP (1), 1989)

Load balancing and task decomposition techniques for parallel implementation of integrated vision systems algorithms. - Alok N. Choudhary; Janak H. Patel (SC, 1989)

Diagnosis and Repair of Memory with Coupling Faults. - Ming-Feng Chang; W. Kent Fuchs; Janak H. Patel (IEEE Trans. Computers, 1989)

Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. - Pinaki Mazumder; Janak H. Patel (IEEE Trans. Computers, 1989)

Experimental evaluation of testability measures for test generation (logic circuits). - Susheel J. Chandra; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

PROOFS: a super fast fault simulator for sequential circuits. - Wu-Tung Cheng; Janak H. Patel (EURO-DAC, 1990)

Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems. - Alok N. Choudhary; Janak H. Patel (ICPP (1), 1990)

A reconfigurable and hierarchical parallel processing architecture: performance results for stereo vision. - Alok N. Choudhary; Subhodev Das; Narendra Ahuja; Janak H. Patel (ICPR (2), 1990)

Parallel implementation and evaluation of motion estimation system algorithms on a distributed memory multiprocessor using knowledge based mappings. - Alok N. Choudhary; Mun K. Leung; Thomas S. Huang; Janak H. Patel (ICPR (2), 1990)

An optimization based approach to the partial scan design problem. - Vivek Chickermane; Janak H. Patel (ITC, 1990)

Error Recovery in Shared Memory Multiprocessors Using Private Caches. - Kun-Lung Wu; W. Kent Fuchs; Janak H. Patel (IEEE Trans. Parallel Distributed Syst., 1990)

A reconfigurable parallel signature analyzer for concurrent error correction in DRAM. - Pinaki Mazumder; Janak H. Patel; Jacob A. Abraham (IEEE J. Solid State Circuits, 1990)

Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. - Srinivas Patil; Prithviraj Banerjee; Janak H. Patel (DAC, 1991)

HITEC: a test generation package for sequential circuits. - Thomas M. Niermann; Janak H. Patel (EURO-DAC, 1991)

An Architectural Level Test Generator for a Hierarchical Design Environment. - Jaushin Lee; Janak H. Patel (FTCS, 1991)

A Fault Oriented Partial Scan Design Approach. - Vivek Chickermane; Janak H. Patel (ICCAD, 1991)

A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. - Jaushin Lee; Janak H. Patel (ICCAD, 1991)

Methods for Reducing Events in Sequential Circuit Fault Simulation. - Elizabeth M. Rudnick; Thomas M. Niermann; Janak H. Patel (ICCAD, 1991)

How Do We Make Parallel Processing a Reality? Bridging the Gap Between Theory and Practice. - Alfred Brenner; Richard F. Freund; R. Stockton Gaines; Rob Kelly; Louis Lome; Richard McAndrew; Alexandru Nicolau; Janak H. Patel; Thomas Probert; John H. Reif; Jorge L. C. Sanz; Howard Jay Siegel; et al. (IPPS, 1991)

Data Prefetching Strategies for Vector Cache Memories. - John W. C. Fu; Janak H. Patel (IPPS, 1991)

Data Prefetching in Multiprocessor Vector Cache Memories. - John W. C. Fu; Janak H. Patel (ISCA, 1991)

ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. - Jaushin Lee; Janak H. Patel (ITC, 1991)

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. - Abhijit Chatterjee; Rabindra K. Roy; Jacob A. Abraham; Janak H. Patel (Digit. Signal Process., 1991)

APT: An Area-Performance-Testability Driven Placement Algorithm. - Sungho Kim; Prithviraj Banerjee; Vivek Chickermane; Janak H. Patel (DAC, 1992)

Hierarchical Test Generation under Intensive Global Functional Constraints. - Jaushin Lee; Janak H. Patel (DAC, 1992)

A comparative study of design for testability methods using high-level and gate-level descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ICCAD, 1992)

E-PROOFS: a CMOS bridging fault simulator. - Gary S. Greenstein; Janak H. Patel (ICCAD, 1992)

Automatic test generation for linear digital systems with bi-level search using matrix transform methods. - Rabindra K. Roy; Abhijit Chatterjee; Janak H. Patel; Jacob A. Abraham; Manuel A. d'Abreu (ICCAD, 1992)

Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs. - Jeff Baxter; Balkrishna Ramkumar; Janak H. Patel (ICPP (1), 1992)

Profiling Based Task Migration. - Jeff Baxter; Janak H. Patel (IPPS, 1992)

Design for Testability Using Architectural Descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ITC, 1992)

An Instruction Sequence Assembling Methodology for Testing Microprocessors. - Jaushin Lee; Janak H. Patel (ITC, 1992)

Diagnostic Fault Simulation of Sequential Circuits. - Elizabeth M. Rudnick; W. Kent Fuchs; Janak H. Patel (ITC, 1992)

Stride directed prefetching in scalar processors. - John W. C. Fu; Janak H. Patel; Bob L. Janssens (MICRO, 1992)

Probe point insertion for at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (VTS, 1992)

An efficient design of embedded memories and their testability analysis using Markov chains. - Pinaki Mazumder; Janak H. Patel (J. Electron. Test., 1992)

PROOFS: a fast, memory-efficient sequential circuit fault simulator. - Thomas M. Niermann; Wu-Tung Cheng; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Test compaction for sequential circuits. - Thomas M. Niermann; Rabindra K. Roy; Janak H. Patel; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Non-Scan Design-for-Testability Techniques for Sequential Circuits. - Vivek Chickermane; Elizabeth M. Rudnick; Prithviraj Banerjee; Janak H. Patel (DAC, 1993)

A Fast and Accurate Gate-Level Transient Fault Simulation Environment. - Hungse Cha; Elizabeth M. Rudnick; Gwan S. Choi; Janak H. Patel; Ravishankar K. Iyer (FTCS, 1993)

Theory and Practice of Sequential Machine Testing and Testability. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (FTCS, 1993)

A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. - Hungse Cha; Janak H. Patel (ICCD, 1993)

Memory Reference Behavior of Compiler Optimized Programs on High Speed. - John W. C. Fu; Janak H. Patel (ICPP (2), 1993)

Efficient Variable Ordering Heuristics for Shared ROBDD. - Pi-Yu Chung; Ibrahim N. Hajj; Janak H. Patel (ISCAS, 1993)

Fast and Accurate CMOS Bridging Fault Simulation. - Jeff Rearick; Janak H. Patel (ITC, 1993)

Impact of high level functional constraints on testability. - Jaushin Lee; Vivek Chickermane; Janak H. Patel (VTS, 1993)

Testability analysis based on structural and behavioral information. - Jaushin Lee; Janak H. Patel (VTS, 1993)

An architectural level test generator based on nonlinear equation solving. - Jaushin Lee; Janak H. Patel (J. Electron. Test., 1993)

NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. - Alok N. Choudhary; Janak H. Patel; Narendra Ahuja (IEEE Trans. Parallel Distributed Syst., 1993)

Microprocessor Testing: Which Technique is Best? (Panel). - Jacob A. Abraham; Sandip Kundu; Janak H. Patel; Manuel A. d'Abreu; Bulent I. Dervisoglu; Marc E. Levitt; Hector R. Sucar; Ron G. Walther (DAC, 1994)

ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. - Steven Parkes; Prithviraj Banerjee; Janak H. Patel (DAC, 1994)

Sequential Circuit Test Generation in a Genetic Algorithm Framework. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (DAC, 1994)

Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. - Elizabeth M. Rudnick; John G. Holm; Daniel G. Saab; Janak H. Patel (EDAC-ETC-EUROASIC, 1994)

Trace Driven Simulation using Sampled Traces. - John W. C. Fu; Janak H. Patel (HICSS (1), 1994)

Fast timing simulation of transient faults in digital circuits. - Abhijit Dharchoudhury; Sung-Mo Kang; Hungse Cha; Janak H. Patel (ICCAD, 1994)

Latch Design for Transient Pulse Tolerance. - Hungse Cha; Janak H. Patel (ICCD, 1994)

Hybrid Resource Management Algorithms for Multicomputer Systems. - Jeff Baxter; John W. C. Fu; Balkrishna Ramkumar; Janak H. Patel (IPPS, 1994)

Addressing design for testability at the architectural level. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Architectural level test generation for microprocessors. - Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

An observability enhancement approach for improved testability and at-speed test. - Elizabeth M. Rudnick; Vivek Chickermane; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Overhead reduction techniques for hierarchical fault simulation. - Eiji Harada; Janak H. Patel (Asian Test Symposium, 1995)

Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. - Elizabeth M. Rudnick; Janak H. Patel (DAC, 1995)

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. - Srikanth Venkataraman; Ismed Hartanto; W. Kent Fuchs; Elizabeth M. Rudnick; Sreejit Chakravarty; Janak H. Patel (DAC, 1995)

Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. - Paul J. Thadikaran; Sreejit Chakravarty; Janak H. Patel (FTCS, 1995)

A new architectural-level fault simulation using propagation prediction of grouped fault-effects. - Michael S. Hsiao; Janak H. Patel (ICCD, 1995)

A parallel algorithm for fault simulation based on PROOFS . - Steven Parkes; Prithviraj Banerjee; Janak H. Patel (ICCD, 1995)

A genetic approach to test application time reduction for full scan and partial scan circuits. - Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1995)

Cyclic stress tests for full scan circuits. - Vinay Dabholkar; Sreejit Chakravarty; J. Najm; Janak H. Patel (VTS, 1995)

A distance reduction approach to design for testability. - Frank F. Hsu; Janak H. Patel (VTS, 1995)

Sequential circuit testability enhancement using a nonscan approach. - Elizabeth M. Rudnick; Vivek Chickermane; Prithviraj Banerjee; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Partial Scan Design Based on Circuit State Information. - Dong Xiang; Srikanth Venkataraman; W. Kent Fuchs; Janak H. Patel (DAC, 1996)

Alternating Strategies for Sequential Circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1996)

On Double Transition Faults as a Delay Fault Model. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (Great Lakes Symposium on VLSI, 1996)

SIGMA: a simulator for segment delay faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1996)

Enhancing high-level control-flow for improved testability. - Frank F. Hsu; Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1996)

Simulation-based techniques for dynamic test sequence compaction. - Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1996)

Testability Insertion in Behavioral Descriptions. - Frank F. Hsu; Elizabeth M. Rudnick; Janak H. Patel (ISSS, 1996)

On Potential Fault Detection in Sequential Circuits. - Elizabeth M. Rudnick; Janak H. Patel; Irith Pomeranz (ITC, 1996)

A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. - Dong Xiang; Janak H. Patel (ITC, 1996)

Improving accuracy in path delay fault coverage estimation. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1996)

Segment delay faults: a new fault model. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VTS, 1996)

Automatic test generation using genetically-engineered distinguishing sequences. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. - Terry Lee; Ibrahim N. Hajj; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1996)

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. - Hungse Cha; Elizabeth M. Rudnick; Janak H. Patel; Ravishankar K. Iyer; Gwan S. Choi (IEEE Trans. Computers, 1996)

Hierarchical test generation under architectural level functional constraints. - Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Sequential circuit test generation using dynamic state traversal. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ED&TC, 1997)

Partial Scan beyond Cycle Cutting. - Gurjeet S. Saund; Michael S. Hsiao; Janak H. Patel (FTCS, 1997)

Fast identification of untestable delay faults using implications. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1997)

Effects of delay models on peak power estimation of VLSI sequential circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ICCAD, 1997)

K2: an estimator for peak sustainable power of VLSI circuits. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ISLPED, 1997)

BART: A Bridging Fault Test Generation for Sequential Circuits. - James P. Cusey; Janak H. Patel (ITC, 1997)

Putting the Squeeze on Test Sequences. - Elizabeth M. Rudnick; Janak H. Patel (ITC, 1997)

Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. - Dilip Krishnaswamy; Prithviraj Banerjee; Elizabeth M. Rudnick; Janak H. Patel (Workshop on Parallel and Distributed Simulation, 1997)

Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. - Charles R. Graham; Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1997)

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. - Dilip Krishnaswamy; Michael S. Hsiao; Vikram Saxena; Elizabeth M. Rudnick; Janak H. Patel; Prithviraj Banerjee (VLSI Design, 1997)

Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. - Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1997)

Diagnostic Test Pattern Generation for Sequential Circuits. - Ismed Hartanto; Vamsi Boppana; Janak H. Patel; W. Kent Fuchs (VTS, 1997)

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1997)

SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. - Dilip Krishnaswamy; Elizabeth M. Rudnick; Janak H. Patel; Prithviraj Banerjee (VTS, 1997)

Static logic implication with application to redundancy identification. - Jian-Kun Zhao; Elizabeth M. Rudnick; Janak H. Patel (VTS, 1997)

Design for Testability Using State Distances. - Frank F. Hsu; Janak H. Patel (J. Electron. Test., 1997)

Improving a nonenumerative method to estimate path delay fault coverage. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A genetic algorithm framework for test generation. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Algorithms to compute bridging fault coverage of IDDQ test sets. - Paul J. Thadikaran; Sreejit Chakravarty; Janak H. Patel (ACM Trans. Design Autom. Electr. Syst., 1997)

High-level variable selection for partial-scan implementation. - Frank F. Hsu; Janak H. Patel (ICCAD, 1998)

Enhancing topological ATPG with high-level information and symbolic techniques. - Fulvio Corno; Janak H. Patel; Elizabeth M. Rudnick; Matteo Sonza Reorda; Roberto Vietti (ICCD, 1998)

Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. - Janak H. Patel (25 Years ISCA: Retrospectives and Reprints, 1998)

Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. - Janak H. Patel (25 Years ISCA: Retrospectives and Reprints, 1998)

Stuck-at fault: a fault model for the next millennium. - Janak H. Patel (ITC, 1998)

Compact two-pattern test set generation for combinational and full scan circuits. - Ilker Hamzaoglu; Janak H. Patel (ITC, 1998)

Partial Scan Selection Based on Dynamic Reachability and Observability Information. - Michael S. Hsiao; Gurjeet S. Saund; Elizabeth M. Rudnick; Janak H. Patel (VLSI Design, 1998)

Diagnostic Simulation of Sequential Circuits Using Fault Sampling. - Srikanth Venkataraman; W. Kent Fuchs; Janak H. Patel (VLSI Design, 1998)

High-Level Controllability and Observability Analysis for Test Synthesis. - Frank F. Hsu; Janak H. Patel (J. Electron. Test., 1998)

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Reducing Test Application Time for Full Scan Embedded Cores. - Ilker Hamzaoglu; Janak H. Patel (FTCS, 1999)

A Test Generator for Segment Delay Faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1999)

An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. - Zbigniew Kalbarczyk; Janak H. Patel; Myeong S. Lee; Ravishankar K. Iyer (VLSI Design, 1999)

New Techniques for Deterministic Test Pattern Generation. - Ilker Hamzaoglu; Janak H. Patel (J. Electron. Test., 1999)

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Computers, 1999)

Efficient Techniques for Dynamic Test Sequence Compaction. - Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Computers, 1999)

Deterministic Test Pattern Generation Techniques for Sequential Circuits. - Ilker Hamzaoglu; Janak H. Patel (ICCAD, 2000)

Enhanced delay defect coverage with path-segments. - Manish Sharma; Janak H. Patel (ITC, 2000)

Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. - Ilker Hamzaoglu; Janak H. Patel (VTS, 2000)

Bounding Circuit Delay by Testing a Very Small Subset of Paths. - Manish Sharma; Janak H. Patel (VTS, 2000)

Test set compaction algorithms for combinational circuits. - Ilker Hamzaoglu; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Dynamic state traversal for sequential circuit test generation. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (ACM Trans. Design Autom. Electr. Syst., 2000)

Peak power estimation of VLSI circuits: new peak power measures. - Michael S. Hsiao; Elizabeth M. Rudnick; Janak H. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A case study on the implementation of the Illinois Scan Architecture. - Frank F. Hsu; Kenneth M. Butler; Janak H. Patel (ITC, 2001)

Testing of critical paths for delay faults. - Manish Sharma; Janak H. Patel (ITC, 2001)

A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. - Jian-Kun Zhao; Jeffrey A. Newquist; Janak H. Patel (VLSI Design, 2001)

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. - Ismed Hartanto; Srikanth Venkataraman; W. Kent Fuchs; Elizabeth M. Rudnick; Janak H. Patel; Sreejit Chakravarty (ACM Trans. Design Autom. Electr. Syst., 2001)

An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. - Amit R. Pandey; Janak H. Patel (DATE, 2002)

Finding a Small Set of Longest Testable Paths that Cover Every Gate. - Manish Sharma; Janak H. Patel (ITC, 2002)

Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . - Amit R. Pandey; Janak H. Patel (VTS, 2002)

Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. - Janak H. Patel; Steven S. Lumetta; Sudhakar M. Reddy (VTS, 2003)

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. - Manish Sharma; Janak H. Patel; Jeff Rearick (VTS, 2003)

The evolution of dependable computing at the University of Illinois. - Ravishankar K. Iyer; William H. Sanders; Janak H. Patel; Zbigniew Kalbarczyk (IFIP Congress Topical Sessions, 2004)

Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. - Mihir A. Shah; Janak H. Patel (ISVLSI, 2004)

Logic BIST with Scan Chain Segmentation. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ITC, 2004)

Logic BIST Using Constrained Scan Cells. - Liyang Lai; Thomas Rinderknecht; Wu-Tung Cheng; Janak H. Patel (VTS, 2004)

What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? - Manish Sharma; Janak H. Patel (VTS, 2004)

Partial Scan Design Based on Circuit State Information and Functional Analysis. - Dong Xiang; Janak H. Patel (IEEE Trans. Computers, 2004)

Hardware Ef.cient LBISTWith Complementary Weights. - Liyang Lai; Janak H. Patel; Thomas Rinderknecht; Wu-Tung Cheng (ICCD, 2005)