On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network. - Nilabjo Dey; Janak Sharda; Utkarsh Saxena; Divya Kaushik; Utkarsh Singh; Debanjan Bhowmik (BioCAS, 2019)

Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning. - Janak Sharda; Nilabjo Dey; Ankesh Jain; Debanjan Bhowmik (ICONS, 2020)

A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning. - Janak Sharda; Ritvik Sharma; Debanjan Bhowmik (ISCAS, 2021)

Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving. - Wantong Li; Qiucheng Wu; Janak Sharda; Shiyu Chang; Shimeng Yu (AICAS, 2022)

On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network. - Varun Bhavin Desai; Divya Kaushik; Janak Sharda; Debanjan Bhowmik (Neuromorph. Comput. Eng., 2022)

Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute. - Janak Sharda; Wantong Li; Qiucheng Wu; Shiyu Chang; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models. - Janak Sharda; Po-Kai Hsu; Shimeng Yu (AICAS, 2024)

Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving. - Janak Sharda; Qiucheng Wu; Shiyu Chang; Shimeng Yu (MWSCAS, 2024)

Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. - Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer 001; Jorge Tomás Gómez; Syed Shakib Sarwar; Ziyun Li; Reid Frederick Pinkham; Barbara De Salvo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor. - Po-Kai Hsu; Sungwon Cho; Janak Sharda; Hyeonwoo Park; Suman Datta; Shimeng Yu (IMW, 2025)

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration. - Wei-Hsing Huang; Janak Sharda; Cheng-Jhih Shih; Yuyao Kong; Faaiq Waqar; Pin-Jun Chen; Yingyan Lin; Shimeng Yu (CoRR, 2025)