Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. - Bishnu Prasad Das; Janakiraman Viraraghavan; Bharadwaj Amrutur; H. S. Jamadagni; N. V. Arvind (VLSI Design, 2008)

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. - Janakiraman Viraraghavan; Bishnu Prasad Das; Bharadwaj Amrutur (VLSI Design, 2008)

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. - Janakiraman Viraraghavan; Bharadwaj Amrutur; V. Visvanathan (J. Low Power Electron., 2008)

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. - Janakiraman Viraraghavan; Bharadwaj Amrutur; V. Visvanathan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Statistical Compact Model Extraction: A Neural Network Approach. - Janakiraman Viraraghavan; Shrinivas J. Pandharpure; Josef Watts (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. - Janakiraman Viraraghavan; Derek Leu; Balaji Jayaraman; Alberto Cestero; Robert Kilker; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; et al. (VLSI Circuits, 2016)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. - Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; et al. (IEEE J. Solid State Circuits, 2018)

Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study. - S. Ashwin Balagopal; Janakiraman Viraraghavan (ISCAS, 2020)

Statistical compact model extraction for skew-normal distributions. - Koduru Revanth; Janakiraman Viraraghavan (IET Circuits Devices Syst., 2020)

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter. - Balaji Vijayakumar; Janakiraman Viraraghavan (ISCAS, 2021)

Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection. - Alfred Festus Davidson; Janakiraman Viraraghavan (IEEE Trans. Educ., 2023)

Geometric Programming Approach to Glitch Minimization via Gate Sizing. - Karthikeyan Muthamizh Vithagan; Vignesh Sundaresha; Janakiraman Viraraghavan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Input-Conditioned Quantisation for ENOB Improvement in CIM ADC Columns Targeting Large-Length Partial Sums. - S. Ashwin Balagopal; Janakiraman Viraraghavan; Balaji Vijayakumar (IEEE Trans. Circuits Syst. II Express Briefs, 2024)