A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points. - Tony Montalvo; C. Angell; David J. McLaurin; Corey Petersen; Eric Fogleman; Janet Brunsilius; Phil Brown; Ege Yetis; Jeff Bray; M. Kessler; Bernard Tenbroek (ISSCC, 2006)

A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC. - Janet Brunsilius; Eric Siragusa; Steve Kosic; Frank Murden; Ege Yetis; Binh Luu; Jeff Bray; Phil Brown; Allen Barlow (ISSCC, 2011)

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration. - Ahmed M. Abdelatty Ali; Hüseyin Dinc; Paritosh Bhoraskar; Christopher Dillon; Scott Puckett; Bryce Gray; Carroll Speir; Jonathan Lanford; David Jarman; Janet Brunsilius; Peter R. Derounian; Brad Jeffries; et al. (ISSCC, 2014)

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration. - Ahmed M. A. Ali; Hüseyin Dinc; Paritosh Bhoraskar; Christopher Dillon; Scott Puckett; Bryce Gray; Carroll Speir; Jonathan Lanford; Janet Brunsilius; Peter R. Derounian; Brad Jeffries; Ushma Mehta; et al. (IEEE J. Solid State Circuits, 2014)

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Steve Kosic; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; et al. (ISSCC, 2017)

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; Nevena Rakuljic; et al. (IEEE J. Solid State Circuits, 2017)

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. - Junhua Shen; Wei-Hung Chen; Efram Burlingame; Stephen Weinreich; Michael Elliott; Stuart McCracken; Jack Kenney; Janet Brunsilius; Anil Korkmaz; Enrique Alvarez-Fontecilla; Nevena Rakuljic; Ushma Mehta; et al. (ISSCC, 2025)