A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. - Jae-Yoon Sim; Jang-Jin Nam; Young-Soo Sohn; Hong-June Park; Chang-Hyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2002)

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications. - Jang-Jin Nam; Hong-June Park (IEICE Trans. Electron., 2005)