A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (ISSCC, 2011)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (IEEE J. Solid State Circuits, 2012)

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)