Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. - Allan Silburt; Ian Perryman; Janick Bergeron; Stacy Nichols; Mario Dufresne; Greg Ward (DAC, 1995)

Panel: Your Core - My Problem? Integration and Verification of IP. - Gabe Moretti; Tim Hopes; Ramesh Narayanaswamy; Nanette Collins; Dave Kelf; Tom Anderson; Janick Bergeron; Ashish Dixit; Peter Flake (DAC, 2001)

Is methodology the highway out of verification hell? - Francine Bacchini; Gabe Moretti; Harry Foster; Janick Bergeron; Masayuki Nakamura; Shrenik Mehta; Laurent Ducousso (DAC, 2005)

Modeling Usable and Reusable Transactors in System Verilog. - Janick Bergeron (VLSI Design, 2005)

Building a verification test plan: trading brute force for finesse. - Janick Bergeron; Harry Foster; Andrew Piziali; Raj Shekher Mitra; Catherine Ahlschlager; Doron Stein (DAC, 2006)

Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test. - Sunil Kakkar; Janick Bergeron; Brian Bailey; Harry Foster; Ian Harris (HLDVT, 2007)

Advances in low power verification. - Janick Bergeron (ISLPED, 2008)

Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips. - Tessil Thomas; Bharath Venkatasubramanian; Dinesh Sthapit; Christopher Gray; Atresh Gummadavelly; Janick Bergeron; Pankaj Mehta; Prabu Thangamuthu (ISPASS, 2022)