The Effect of Choosing the Switches for Rearrangements in Switching Networks. - Andrzej Jajszczyk; Janusz Rajski (IEEE Trans. Commun., 1980)

The detection of small size multiple faults by single fault test sets n programmable logic arrays. - Janusz Rajski; Jerzy Tyszer (Fehlertolerierende Rechensysteme, 1984)

Testing Properties and Applications of Inverter-Free PLA's. - Vinod K. Agarwal; Janusz Rajski (ITC, 1985)

Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1985)

The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1986)

Testing and Applications of Inverter-Free PLAs. - Janusz Rajski; Vinod K. Agarwal (IEEE Des. Test, 1987)

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits. - Fadi Maamari; Janusz Rajski (FTCS, 1988)

GEMINI-a logic system for fault diagnosis based on set functions. - Janusz Rajski (FTCS, 1988)

Parallel PLA fault simulation based on Boolean vector operations. - Eli Chiprout; Janusz Rajski; Markus Robinson (ICCAD, 1988)

A fault simulation method based on stem regions. - Fadi Maamari; Janusz Rajski (ICCAD, 1988)

A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. - Stephen Pateras; Janusz Rajski (ICCD, 1988)

On Multiple Fault Coverage and Aliasing Probability Measures. - Henry Cox; André Ivanov; Vinod K. Agarwal; Janusz Rajski (ITC, 1988)

Stuck-Open and Transition Fault Testing in CMOS Complex Gates. - Henry Cox; Janusz Rajski (ITC, 1988)

Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Janusz Rajski (ITC, 1988)

An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. - Markus Robinson; Janusz Rajski (ITC, 1988)

A method of fault analysis for test generation and fault diagnosis. - Henry Cox; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Testing of Glue Logic Interconnects Using Boundary Scan Architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Janusz Rajski; Benoit Nadeau-Dostie (ITC, 1989)

On the Diagnostic Resolution of Signature Analysis. - Janusz Rajski; Jerzy Tyszer; Babak Salimi (ICCAD, 1990)

A Method for Concurrent Decomposition and Factorization of Boolean Expressions. - Jagadeesh Vasudevamurthy; Janusz Rajski (ICCAD, 1990)

Empirical failure analysis and validation of fault models in CMOS VLSI. - Ashish Pancholy; Janusz Rajski; Larry J. McNaughton (ITC, 1990)

A method to calculate necessary assignments in algorithmic test pattern generation. - Janusz Rajski; Henry Cox (ITC, 1990)

Testability preserving transformations in multi-level logic synthesis. - Janusz Rajski; Jagadeesh Vasudevamurthy (ITC, 1990)

A method of fault simulation based on stem regions. - Fadi Maamari; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. - Stephen Pateras; Janusz Rajski (DAC, 1991)

Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. - Stephen Pateras; Janusz Rajski (ITC, 1991)

On the diagnostic properties of linear feedback shift registers. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A fault-tolerant array processor designed for testability and self-reconfiguration. - Ajai Jain; Babu Mandava; Janusz Rajski; Nicholas C. Rumin (IEEE J. Solid State Circuits, 1991)

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. - Sybille Hellebrand; Steffen Tarnick; Bernard Courtois; Janusz Rajski (ITC, 1992)

Recent advances in logic synthesis with testability. - Janusz Rajski; Jagadeesh Vasudevamurthy; Aiman El-Maleh (VTS, 1992)

Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. - Ashish Pancholy; Janusz Rajski; Larry J. McNaughton (IEEE Des. Test Comput., 1992)

BIST of PCB interconnects using boundary-scan architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Benoit Nadeau-Dostie; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

The testability-preserving concurrent decomposition and factorization of Boolean expressions. - Janusz Rajski; Jagadeesh Vasudevamurthy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Accumulator-Based Compaction of Test Responses. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1993)

Recursive Pseudoexhaustive Test Pattern Generation. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1993)

The dynamic reduction of fault simulation. - Fadi Maamari; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Test responses compaction in accumulators with rotate carry adders. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Test pattern generation based on arithmetic operations. - Sanjay Gupta; Janusz Rajski; Jerzy Tyszer (ICCAD, 1994)

On necessary and nonconflicting assignments in algorithmic test pattern generation. - Henry Cox; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On Test Set Preservation of Retimed Circuits. - Aiman H. El-Maleh; Thomas E. Marchok; Janusz Rajski; Wojciech Maly (DAC, 1995)

Software Accelerated Functional Fault Simulation for Data-Path Architectures. - Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 1995)

Complexity of sequential ATPG. - Thomas E. Marchok; Aiman El-Maleh; Wojciech Maly; Janusz Rajski (ED&TC, 1995)

On testable multipliers for fixed-width data path architectures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ICCAD, 1995)

Hierarchical Functional-Fault Simulation for High-Level Synthesis. - Mark Kassab; Janusz Rajski; Jerzy Tyszer (ITC, 1995)

Arithmetic built-in self test for high-level synthesis. - Nilanjan Mukherjee 001; H. Kassab; Janusz Rajski; Jerzy Tyszer (VTS, 1995)

Fault coverage analysis of RAM test algorithms. - Marc D. Riedel; Janusz Rajski (VTS, 1995)

Decompression of test data using variable-length seed LFSRs. - Nadime Zacharia; Janusz Rajski; Jerzy Tyszer (VTS, 1995)

Testability Implications of Performance-Driven Logic Synthesis. - Thomas E. Marchok; Aiman H. El-Maleh; Janusz Rajski; Wojciech Maly (IEEE Des. Test Comput., 1995)

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. - Sybille Hellebrand; Janusz Rajski; Steffen Tarnick; Srikanth Venkataraman; Bernard Courtois (IEEE Trans. Computers, 1995)

Delay-fault testability preservation of the concurrent decomposition and factorization transformations. - Aiman H. El-Maleh; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Multiplicative Window Generators of Pseudo-random Test Vectors. - Janusz Rajski; Jerzy Tyszer (ED&TC, 1996)

Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. - Nagesh Tamarapalli; Janusz Rajski (ITC, 1996)

Two-Dimensional Test Data Decompressor for Multiple Scan Designs. - Nadime Zacharia; Janusz Rajski; Jerzy Tyszer; John A. Waicukauski (ITC, 1996)

Hardware-Software Co-Design for Test: It's the Last Straw! - J. El-Ziq; Najmi T. Jarwala; Niraj K. Jha; Peter Marwedel; Christos A. Papachristou; Janusz Rajski; John W. Sheppard (VTS, 1996)

A self-driven test structure for pseudorandom testing of non-scan sequential circuits. - Fidel Muradali; Janusz Rajski (VTS, 1996)

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. - Sanjay Gupta; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1996)

On Linear Dependencies in Subspaces of LFSR-Generated Sequences. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1996)

A complexity analysis of sequential ATPG. - Thomas E. Marchok; Aiman H. El-Maleh; Wojciech Maly; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

STARBIST: Scan Autocorrelated Random Pattern Generation. - Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski; Malgorzata Marek-Sadowska (DAC, 1997)

Parameterizable Testing Scheme for FIR Filters. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ITC, 1997)

Fault Diagnosis in Scan-Based BIST. - Janusz Rajski; Jerzy Tyszer (ITC, 1997)

Scan-Encoded Test Pattern Generation for BIST. - Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 1997)

Systems On Silicon: Design and Test Challenges. - J. Borel; M. Cecchini; C. Malipeddi; Janusz Rajski; Yervant Zorian (VTS, 1997)

Design of Testable Multipliers for Fixed-Width Data Paths. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1997)

Behavior and testability preservation under the retiming transformation. - Aiman H. El-Maleh; Thomas E. Marchok; Janusz Rajski; Wojciech Maly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Arithmetic built-in self-test for DSP cores. - Katarzyna Radecka; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. - Aiman H. El-Maleh; Mark Kassab; Janusz Rajski (DAC, 1998)

Modular logic built-in self-test for IP cores. - Janusz Rajski; Jerzy Tyszer (ITC, 1998)

Automated synthesis of large phase shifters for built-in self-test. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (ITC, 1998)

Design of Phase Shifters for BIST Applications. - Janusz Rajski; Jerzy Tyszer (VTS, 1998)

Test Data Decompression for Multiple Scan Designs with Boundary Scan. - Janusz Rajski; Jerzy Tyszer; Nadime Zacharia (IEEE Trans. Computers, 1998)

Logic BIST for large industrial designs: real issues and case studies. - Graham Hetherington; Tony Fryars; Nagesh Tamarapalli; Mark Kassab; Abu S. M. Hassan; Janusz Rajski (ITC, 1999)

Synthesis of pattern generators based on cellular automata with phase shifters. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (ITC, 1999)

STAR-ATPG: a high speed test pattern generator for large scan designs. - Kuo-Hui Tsai; Tompson; Janusz Rajski; Malgorzata Marek-Sadowska (ITC, 1999)

Built-In Self-Test for Systems on Silicon. - Janusz Rajski; Jerzy Tyszer; Sanjay Patel (VLSI Design, 1999)

Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. - Janusz Rajski; Grzegorz Mrugalski; Jerzy Tyszer (VTS, 1999)

Testing of telecommunications hardware [Guest Editorial]. - Janusz Rajski; Jerzy Tyszer (IEEE Commun. Mag., 1999)

Diagnosis of Scan Cells in BIST Environment. - Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1999)

Self-test methodology for at-speed test of crosstalk in chip interconnects. - Xiaoliang Bai; Sujit Dey; Janusz Rajski (DAC, 2000)

Improving the Proportion of At-Speed Tests in Scan BIST. - Yu Huang 005; Irith Pomeranz; Sudhakar M. Reddy; Janusz Rajski (ICCAD, 2000)

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (VTS, 2000)

Cellular automata-based test pattern generators with phase shifters. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Automated synthesis of phase shifters for built-in self-testapplications. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Star test: the theory and its applications. - Kun-Han Tsai; Janusz Rajski; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

DFT for High-Quality Low Cost Manufacturing Test. - Janusz Rajski (Asian Test Symposium, 2001)

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. - John T. Chen; Jitendra Khare; Ken Walker; Saghir A. Shaikh; Janusz Rajski; Wojciech Maly (ITC, 2001)

On static test compaction and test pattern ordering for scan designs. - Xijiang Lin; Janusz Rajski; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

Enabling Embedded Memory Diagnosis via Test Response Compression. - John T. Chen; Wojciech Maly; Janusz Rajski; Omar Kebichi; Jitendra Khare (VTS, 2001)

Testing Schemes for FIR Filter Structures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2001)

Finding a Common Fault Response for Diagnosis during Silicon Debug. - Irith Pomeranz; Janusz Rajski; Sudhakar M. Reddy (DATE, 2002)

Conflict driven techniques for improving deterministic test pattern generation. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (ICCAD, 2002)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Janusz Rajski (ASP-DAC/VLSI Design, 2002)

Innovations in Test Automation. - J. Borel; Anand Raghunathan; Jim Sproch; Michael Howells; Janusz Rajski (VTS, 2002)

On Compacting Test Response Data Containing Unknown Values. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Jerzy Tyszer (ICCAD, 2003)

Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. - Janusz Rajski; Jerzy Tyszer (ICCD, 2003)

Multiple Fault Diagnosis Using n-Detection Tests. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2003)

Impact of Multiple-Detect Test Patterns on Product Quality. - Brady Benware; Chris Schuermyer; Sreenevasan Ranganathan; Robert Madge; Prabhu Krishnamurthy; Nagesh Tamarapalli; Kun-Han Tsai; Janusz Rajski (ITC, 2003)

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. - Frank Poehl; Matthias Beck; Ralf Arnold; Peter Muhmenthaler; Nagesh Tamarapalli; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2003)

Test Challenges of Nanometer Technology. - Janusz Rajski (ITC, 2003)

Convolutional Compaction of Test Responses. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (ITC, 2003)

An Efficient and Effective Methodology on the Multiple Fault Diagnosis. - Zhiyuan Wang; Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 2003)

High Speed Ring Generators and Compactors of Test Data. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (VTS, 2003)

High-Frequency, At-Speed Scan Testing. - Xijiang Lin; Ron Press; Janusz Rajski; Paul Reuter; Thomas Rinderknecht; Bruce Swanson; Nagesh Tamarapalli (IEEE Des. Test Comput., 2003)

2D Test Sequence Generators. - Grzegorz Mrugalski; Jerzy Tyszer; Janusz Rajski (IEEE Des. Test Comput., 2003)

Embedded Deterministic Test for Low-Cost Manufacturing. - Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Nagesh Tamarapalli; Jerzy Tyszer; Jun Qian (IEEE Des. Test Comput., 2003)

Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. - Janusz Rajski; Jerzy Tyszer (J. Electron. Test., 2003)

Compactor Independent Direct Diagnosis. - Wu-Tung Cheng; Kun-Han Tsai; Yu Huang 005; Nagesh Tamarapalli; Janusz Rajski (Asian Test Symposium, 2004)

Nanometer Design: What are the Requirements for Manufacturing Test? - Janusz Rajski; Kan Thapar (DATE, 2004)

Diagnosis of Hold Time Defects. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2004)

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. - Brady Benware; Cam Lu; John Van Slyke; Prabhu Krishnamurthy; Robert Madge; Martin Keim; Mark Kassab; Janusz Rajski (ITC, 2004)

Realizing High Test Quality Goals with Smart Test Resource Usage. - Xinli Gu; Cyndee Wang; Abby Lee; Bill Eklow; Kun-Han Tsai; Jan Arild Tofte; Mark Kassab; Janusz Rajski (ITC, 2004)

Fault Diagnosis in Designs with Convolutional Compactors. - Grzegorz Mrugalski; Chen Wang 014; Artur Pogiel; Jerzy Tyszer; Janusz Rajski (ITC, 2004)

Embedded Test for Low Cost Manufacturing. - Janusz Rajski; Nilanjan Mukherjee 001; Jerzy Tyszer; Thomas Rinderknecht (VLSI Design, 2004)

Planar High Performance Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VTS, 2004)

Ring generators - new devices for embedded test applications. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Embedded deterministic test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Propagation delay fault: a new fault model to test delay faults. - Xijiang Lin; Janusz Rajski (ASP-DAC, 2005)

Embedded Test Technology - Brief History, Current Status, and Future Directions. - Janusz Rajski (Asian Test Symposium, 2005)

Defect Aware Test Patterns. - Huaxing Tang; Gang Chen 011; Sudhakar M. Reddy; Chen Wang 014; Janusz Rajski; Irith Pomeranz (DATE, 2005)

A unified fault model and test generation procedure for interconnect opens and bridges. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Piet Engelke; Bernd Becker 001 (ETS, 2005)

Convolutional compaction-driven diagnosis of scan failures. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (ETS, 2005)

Compressed pattern diagnosis for scan chain failures. - Yu Huang 005; Wu-Tung Cheng; Janusz Rajski (ITC, 2005)

Diagnosis with convolutional compactors in presence of unknown states. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2005)

Test compression - real issues and matching solutions. - Janusz Rajski (ITC, 2005)

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. - Huaxing Tang; Chen Wang 014; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Irith Pomeranz (VLSI Design, 2005)

Synthesis of X-Tolerant Convolutional Compactors. - Janusz Rajski; Jerzy Tyszer (VTS, 2005)

Finite memory test response compactors for embedded test applications. - Janusz Rajski; Jerzy Tyszer; Chen Wang 014; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Delay-fault diagnosis using timing information. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

At-Speed Testing with Timing Exceptions and Constraints-Case Studies. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Takeo Kobayashi; Janusz Rajski; Bruce Swanson; Darryl Walters; Yasuo Sato; Toshiharu Asaka; Takashi Aikyo (ATS, 2006)

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. - Xijiang Lin; Kun-Han Tsai; Chen Wang 014; Mark Kassab; Janusz Rajski; Takeo Kobayashi; Randy Klingenberg; Yasuo Sato; Shuji Hamada; Takashi Aikyo (ATS, 2006)

A test pattern ordering algorithm for diagnosis with truncated fail data. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (DAC, 2006)

Test response compactor with programmable selector. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (DAC, 2006)

Convolutional Compactors with Variable Polynomials. - Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2006)

Delay Fault Diagnosis for Non-Robust Test. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Zhiyuan Wang; Kun-Han Tsai; Janusz Rajski (ISQED, 2006)

Diagnosis with Limited Failure Information. - Yu Huang 005; Wu-Tung Cheng; Nagesh Tamarapalli; Janusz Rajski; Randy Klingenberg; Will Hsu; Yuan-Shih Chen (ITC, 2006)

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. - Martin Keim; Nagesh Tamarapalli; Huaxing Tang; Manish Sharma; Janusz Rajski; Chris Schuermyer; Brady Benware (ITC, 2006)

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ITC, 2006)

X-Press Compactor for 1000x Reduction of Test Data. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2006)

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. - Santiago Remersaro; Xijiang Lin; Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (ITC, 2006)

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2006)

The Impacts of Untestable Defects on Transition Fault Testing. - Xijiang Lin; Janusz Rajski (VTS, 2006)

Modular Compactor of Test Responses. - Wojciech Rajski; Janusz Rajski (VTS, 2006)

Scan Tests with Multiple Fault Activation Cycles for Delay Faults. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (VTS, 2006)

High Performance Dense Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2006)

Analysis and methodology for multiple-fault diagnosis. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Test Generation for Timing-Critical Transition Faults. - Xijiang Lin; Mark Kassab; Janusz Rajski (ATS, 2007)

Test Generation in the Presence of Timing Exceptions and Constraints. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Janusz Rajski (DAC, 2007)

New Test Data Decompressor for Low Power Applications. - Grzegorz Mrugalski; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (DAC, 2007)

Logic Diagnosis and Yield Learning. - Janusz Rajski (DDECS, 2007)

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. - Huaxing Tang; Manish Sharma; Janusz Rajski; Martin Keim; Brady Benware (ETS, 2007)

Low Shift and Capture Power Scan Tests. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2007)

Low Power Embedded Deterministic Test. - Dariusz Czysz; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (VTS, 2007)

Silicon Evaluation of Static Alternative Fault Models. - Chris Schuermyer; Jewel Pangilinan; Jay Jahangiri; Martin Keim; Janusz Rajski; Brady Benware (VTS, 2007)

Scan-Based Tests with Low Switching Activity. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (IEEE Des. Test Comput., 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Isolation of Failing Scan Cells through Convolutional Test Response Compaction. - Grzegorz Mrugalski; Janusz Rajski; Chen Wang 014; Artur Pogiel; Jerzy Tyszer (J. Electron. Test., 2007)

Enhancing delay fault coverage through low-power segmented scan. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Bashir M. Al-Hashimi (IET Comput. Digit. Tech., 2007)

Fault Diagnosis With Convolutional Compactors. - Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Test Power Reduction by Blocking Scan Cell Outputs. - Xijiang Lin; Janusz Rajski (ATS, 2008)

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. - Santiago Remersaro; Janusz Rajski; Thomas Rinderknecht; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

Low Power Scan Shift and Capture in the EDT Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

Test Generation for Interconnect Opens. - Xijiang Lin; Janusz Rajski (ITC, 2008)

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. - Dariusz Czysz; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Improving the Resolution of Single-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

N-distinguishing Tests for Enhanced Defect Diagnosis. - Gang Chen 011; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2009)

A scalable method for the generation of small test sets. - Santiago Remersaro; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (DATE, 2009)

We Have Got Compression, What Next? - Janusz Rajski (ETS, 2009)

Compression based on deterministic vector clustering of incompatible test cubes. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (ITC, 2009)

Fault diagnosis for embedded read-only memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2009)

High-Speed On-Chip Event Counters for Embedded Systems. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Defect Aware to Power Conscious Tests - The New DFT Landscape. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Highly X-Tolerant Selective Compaction of Test Responses. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (VTS, 2009)

Low-Power Scan Operation in Test Compression Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Timing-Aware Multiple-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Adaptive Low Shift Power Test Pattern Generator for Logic BIST. - Xijiang Lin; Janusz Rajski (Asian Test Symposium, 2010)

Low power compression of incompatible test cubes. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (ITC, 2010)

Dynamic channel allocation for higher EDT compression in SoC designs. - Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ITC, 2010)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

At-speed scan test with low switching activity. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Mark Kassab (VTS, 2010)

On Compaction Utilizing Inter and Intra-Correlation of Unknown States. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Low Power Decompressor and PRPG with Constant Value Broadcast. - Michal Filipek; Yoshiaki Fukui; Hiroyuki Iwata; Grzegorz Mrugalski; Janusz Rajski; Masahiro Takakura; Jerzy Tyszer (Asian Test Symposium, 2011)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Jakub Janicki (Asian Test Symposium, 2011)

Fault Diagnosis in Memory BIST Environment with Non-march Tests. - Grzegorz Mrugalski; Artur Pogiel; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Pawel Urbanek (Asian Test Symposium, 2011)

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. - Brady Benware; Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (ETS, 2011)

Reduced ATE Interface for High Test Data Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ETS, 2011)

Cell-aware analysis for small-delay effects and production test results from different fault models. - Friedrich Hapke; Jürgen Schlöffel; Wilfried Redemund; Andreas Glowatz; Janusz Rajski; Michael Reese; J. Rearick; Jason Rivers (ITC, 2011)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. - Jakub Janicki; Jerzy Tyszer; Avijit Dutta; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2011)

Low power compression utilizing clock-gating. - Janusz Rajski; Elham K. Moghaddam; Sudhakar M. Reddy (ITC, 2011)

Ring Generator: An Ultimate Linear Feedback Shift Register. - Nilanjan Mukherjee 001; Janusz Rajski; Grzegorz Mrugalski; Artur Pogiel; Jerzy Tyszer (Computer, 2011)

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. - Brady Benware; Grzegorz Mrugalski; Artur Pogiel; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (J. Electron. Test., 2011)

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

BIST-Based Fault Diagnosis for Read-Only Memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

On Utilizing Test Cube Properties to Reduce Test Data Volume Further. - Xijiang Lin; Janusz Rajski (Asian Test Symposium, 2012)

Bandwidth-aware test compression logic for SoC designs. - Jakub Janicki; Jerzy Tyszer; Grzegorz Mrugalski; Janusz Rajski (ETS, 2012)

Low power test application with selective compaction in VLSI designs. - Dariusz Czysz; Janusz Rajski; Jerzy Tyszer (ITC, 2012)

Cell-aware Production test results from a 32-nm notebook processor. - Friedrich Hapke; Michael Reese; Jason Rivers; A. Over; V. Ravikumar; Wilfried Redemund; Andreas Glowatz; Jürgen Schlöffel; Janusz Rajski (ITC, 2012)

Low power programmable PRPG with enhanced fault coverage gradient. - Jedrzej Solecki; Jerzy Tyszer; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2012)

Test generator with preselected toggling for low power built-in self-test. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Benoit Nadeau-Dostie (VTS, 2012)

EDT Bandwidth Management in SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Thomas Rinderknecht (Asian Test Symposium, 2013)

New test compression scheme based on low power BIST. - Jerzy Tyszer; Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ETS, 2013)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

On the generation of compact test sets. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Chen Wang 014 (ITC, 2013)

Fault diagnosis of TSV-based interconnects in 3-D stacked designs. - Janusz Rajski; Jerzy Tyszer (ITC, 2013)

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. - Janusz Rajski; Miodrag Potkonjak; Adit D. Singh; Abhijit Chatterjee; Zain Navabi; Matthew R. Guthaus; Sezer Gören 001 (VLSI-SoC, 2013)

On Deploying Scan Chains for Data Storage in Test Compression Environment. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Des. Test, 2013)

Test Time Reduction in EDT Bandwidth Management for SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Low Power Test Compression with Programmable Broadcast-Based Control. - Sylwester Milewski; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ATS, 2014)

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. - Maciej Trawka; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ATS, 2014)

On Using Implied Values in EDT-based Test Compression. - Marcin Gebala; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 2014)

Quality assurance in memory built-in self-test tools. - Albert Au; Artur Pogiel; Janusz Rajski; Piotr Sydow; Jerzy Tyszer; Justyna Zawada (DDECS, 2014)

Cell-aware experiences in a high-quality automotive test suite. - Friedrich Hapke; Ralf Arnold; Matthias Beck; M. Baby; S. Straehle; J. F. Goncalves; A. Panait; R. Behr; Gwenolé Maugard; A. Prashanthi; Juergen Schloeffel; Wilfried Redemund; et al. (ETS, 2014)

Using dynamic shift to reduce test data volume in high-compression designs. - Xijiang Lin; Mark Kassab; Janusz Rajski (ETS, 2014)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)

Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? - Jacob A. Abraham; Xinli Gu; Teresa MacLaurin; Janusz Rajski; Paul G. Ryan; Dimitris Gizopoulos; Matteo Sonza Reorda (VTS, 2014)

Cell-Aware Test. - Friedrich Hapke; Wilfried Redemund; Andreas Glowatz; Janusz Rajski; Michael Reese; Marek Hustava; Martin Keim; Juergen Schloeffel; Anja Fast (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. - Xijiang Lin; Wu-Tung Cheng; Janusz Rajski (ATS, 2015)

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. - Grzegorz Mrugalski; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Chen Wang 014 (ATS, 2015)

Design for low test pattern counts. - Haluk Konuk; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Deepak Solanki; Jerzy Tyszer; Justyna Zawada (DAC, 2015)

Embedded deterministic test points for compact cell-aware tests. - Cesar Acero; Derek Feltham; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Marek Patyra; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2015)

A deterministic BIST scheme based on EDT-compressed test patterns. - Grzegorz Mrugalski; Janusz Rajski; Lukasz Rybak 001; Jedrzej Solecki; Jerzy Tyszer (ITC, 2015)

Hybrid Hierarchical and Modular Tests for SoC Designs. - Guoliang Li 004; Jun Qian; Qinfu Yang; Yuan Zuo; Rui Li 084; Yu Huang 005; Mark Kassab; Janusz Rajski (NATW, 2015)

Clock-domain-aware test for improving pattern compression. - Kun-Han Tsai; Janusz Rajski (VLSI-DAT, 2015)

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (VLSID, 2015)

Innovative practices session 11C: Advanced scan methodologies [3 presentations]. - Janusz Rajski; Nilanjan Mukherjee 001 (VTS, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low-Power Programmable PRPG With Test Compression Capabilities. - Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On Test Points Enhancing Hardware Security. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ATS, 2016)

Transistor stuck-on fault detection tests for digital CMOS circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (ETS, 2016)

Minimal area test points for deterministic patterns. - Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Sudhakar M. Reddy; Janusz Rajski; Jerzy Tyszer (ITC, 2016)

Test point insertion in hybrid test compression/LBIST architectures. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2016)

Digital Testing of ICs for Automotive Applications. - Nilanjan Mukherjee 001; Janusz Rajski (VLSID, 2016)

On New Test Points for Compact Cell-Aware Tests. - Cesar Acero; Derek Feltham; Marek Patyra; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Des. Test, 2016)

ROM fault diagnosis for O(n2) test algorithms. - Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2017)

Full-scan LBIST with capture-per-cycle hybrid test points. - Sylwester Milewski; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (ITC, 2017)

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. - Grzegorz Mrugalski; Janusz Rajski; Lukasz Rybak 001; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Trimodal Scan-Based Test Paradigm. - Grzegorz Mrugalski; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hypercompression of Test Patterns. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (ITC, 2018)

DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. - Will Howell; Friedrich Hapke; Edward Brazil; Srikanth Venkataraman; R. Datta; Andreas Glowatz; Wilfried Redemund; J. Schmerberg; Anja Fast; Janusz Rajski (ITC, 2018)

Deterministic Stellar BIST for In-System Automotive Test. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (ITC, 2018)

On New Class of Test Points and Their Applications. - Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2018)

Staggered ATPG with capture-per-cycle observation test points. - Yingdi Liu; Janusz Rajski; Sudhakar M. Reddy; Jedrzej Solecki; Jerzy Tyszer (VTS, 2018)

Hardware Protection via Logic Locking Test Points. - Michael Chen; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Test Time and Area Optimized BrST Scheme for Automotive ICs. - Nilanjan Mukherjee 001; Jerzy Tyszer; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki (ITC, 2019)

On Cyclic Scan Integrity Tests for EDT-based Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (VTS, 2019)

Logic BIST With Capture-Per-Clock Hybrid Test Points. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Test Sequence-Optimized BIST for Automotive Applications. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (ETS, 2020)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. - Jean-François Côté; Mark Kassab; Wojciech Janiszewski; Ricardo Rodrigues 008; Reinhard Meier; Bartosz Kaczmarek; Peter Orlando; Geir Eide; Janusz Rajski; Glenn Colón-Bonet; Naveen Mysore; Ya Yin; et al. (ITC, 2020)

X-Tolerant Tunable Compactor for In-System Test. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wldarczak (ITC, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Effective Design of Layout-Friendly EDT Decompressor. - Yu Huang 005; Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Jeffrey Mayer (VTS, 2020)

Scan Integrity Tests for EDT Compression. - Wu-Tung Cheng; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Des. Test, 2020)

Low Cost Hypercompression of Test Data. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Deterministic Stellar BIST for Automotive ICs. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Convolutional Compaction-Based MRAM Fault Diagnosis. - Bartosz Grzelak; Martin Keim; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ETS, 2021)

On Reduction of Deterministic Test Pattern Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (ITC, 2021)

Defect-Oriented Test: Effectiveness in High Volume Manufacturing. - Friedrich Hapke; Will Howell; Peter C. Maxwell; Edward Brazil; Srikanth Venkataraman; Rudrajit Dutta; Andreas Glowatz; Anja Fast; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Autonomous Scan Patterns for Laser Voltage Imaging. - Wu-Tung Cheng; Sylwester Milewski; Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (IEEE Trans. Emerg. Top. Comput., 2021)

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Time and Area Optimized Testing of Automotive ICs. - Nilanjan Mukherjee 001; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2021)

X-Masking for In-System Deterministic Test. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (ETS, 2022)

Test Generation for an Iterative Design Flow with RTL Changes. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2022)

DIST: Deterministic In-System Test with X-masking. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2022)

Hardware Root of Trust for SSN-basedDFT Ecosystems. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2022)

Fast Test Generation for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (VTS, 2022)

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. - Shi-Xuan Zheng; Chung-Yu Yeh; Kuen-Jong Lee; Chen Wang 014; Wu-Tung Cheng; Mark Kassab; Janusz Rajski; Sudhakar M. Reddy (VTS, 2022)

LBIST for Automotive ICs With Enhanced Test Generation. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hybrid Ring Generators for In-System Test Applications. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ETS, 2023)

A New Static Compaction of Deterministic Test Sets. - Stephan Eggersglüß; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Lightweight True Random Number Generator for Root of Trust Applications. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

X-Masking for Deterministic In-System Tests. - Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Delay Monitoring Under Different PVT Corners for Test and Functional Operation. - Hari Addepalli; Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2024)

Test Data Encryption with a New Stream Cipher. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (ITC, 2024)

Deterministic In-Fleet Scan Test for a Cloud Computing Platform. - Dan Trock; Subramanian Mahadevan; Nilanjan Mukherjee 001; Lee Harrison; Janusz Rajski; Jerzy Tyszer (ITC, 2024)

Generation of Two-Cycle Tests for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

H2B: Crypto Hash Functions Based on Hybrid Ring Generators. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

The Future of Design for Test and Silicon Lifecycle Management. - Janusz Rajski; Vivek Chickermane; Jean-François Côté; Stephan Eggersglüß; Nilanjan Mukherjee 001; Jerzy Tyszer (IEEE Des. Test, 2024)

VLSI Test and Trust Roundtable. - Ramesh Karri; Janusz Rajski; Rob Aitken; Subhasish Mitra; Mark Tehranipoor (IEEE Des. Test, 2024)

Identification of Failing Flip-Flops with Triangular Test Response Compaction. - Grzegorz Mrugalski; Janusz Rajski; Maciej Trawka; Jerzy Tyszer (ETS, 2025)

Timing-Verification Test Generation Targeting Small Delay Defects. - Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Kun-Han Tsai; Janusz Rajski (VTS, 2025)

A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Hybrid Ring Generators for In-System Testing. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (J. Electron. Test., 2025)

On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers. - Janusz Rajski; Maciej Trawka; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)