Immediate optimization for compressed transport triggered architecture instructions. - Jari Heikkinen; Tommi Rantanen; Andrea G. M. Cilio; Jarmo Takala; Henk Corporaal (SoC, 2003)

Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. - Jari Heikkinen; Tommi Rantanen; Andrea G. M. Cilio; Jarmo Takala; Henk Corporaal (IWSOC, 2003)

Design of Transport Triggered Architecture Processors for Wireless Encryption. - Panu Hämäläinen; Jari Heikkinen; Marko Hännikäinen; Timo D. Hämäläinen (DSD, 2005)

Dictionary-based program compression on transport triggered architectures. - Jari Heikkinen; Andrea G. M. Cilio; Jarmo Takala; Henk Corporaal (ISCAS (2), 2005)

Programmability in Dictionary-Based Compression. - Jari Heikkinen; Jarmo Takala (SoC, 2006)

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. - Teemu Pitkänen; Risto Mäkinen; Jari Heikkinen; Tero Partanen; Jarmo Takala (SAMOS, 2006)

Effects of program compression. - Jari Heikkinen; Jarmo Takala (J. Syst. Archit., 2007)

Program compression in long instruction word application-specific instruction-set processors. - Jari Heikkinen (2007)

Dictionary-based program compression on customizable processor architectures. - Jari Heikkinen; Jarmo Takala; Henk Corporaal (Microprocess. Microsystems, 2009)