A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology. - Fadi H. Gebara; Jeremy D. Schaub; Tuyet Nguyen; Jarom Peña; Ivan Vo; David Boerstler; Kevin J. Nowka (ISSCC, 2007)

On-chip jitter and oscilloscope circuits using an asynchronous sample clock. - Jeremy D. Schaub; Fadi H. Gebara; Tuyet Nguyen; Ivan Vo; Jarom Peña; Dhruva J. Acharyya (ESSCIRC, 2008)

Voltage droop reduction using throttling controlled by timing margin feedback. - Michael S. Floyd; Alan J. Drake; Robert W. Berry; Harold Chase; Richard L. Willaman; Jarom Peña (VLSIC, 2012)