Test Scheduling for SoC under Power Constraints. - Jaroslav Skarvada (DDECS, 2006)

Power Conscious RTL Test Scheduling. - Jaroslav Skarvada; Zdenek Kotásek; Tomas Herrman (DSD, 2008)

Instruction-based development: From evolution to generic structures of digital circuits. - Michal Bidlo; Jaroslav Skarvada (Int. J. Knowl. Based Intell. Eng. Syst., 2008)

Testability analysis based on the identification of testable blocks with predefined properties. - Jaroslav Skarvada; Zdenek Kotásek; Tomas Herrman (Microprocess. Microsystems, 2008)

Reduction of power dissipation through parallel optimization of test vector and scan register sequences. - Zdenek Kotásek; Jaroslav Skarvada; Josef Strnadel (DDECS, 2010)

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. - Zdenek Kotásek; Jaroslav Skarvada; Josef Strnadel (DSD, 2010)

The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. - Jaroslav Skarvada; Zdenek Kotásek; Josef Strnadel (ICES, 2010)