Technology Mapping for Large Complex PLDs. - Jason Helge Anderson; Stephen Dean Brown (DAC, 1998)

An LPGA with Foldable PLA-style Logic Blocks. - Jason Helge Anderson; Stephen Dean Brown (FPGA, 1998)

A Placement Algorithm for FPGA Designs with Multiple I/O Standards. - Jason Helge Anderson; Jim Saunders; Sudip Nag; Chari Madabhushi; Rajeev Jayaraman (FPL, 2000)

Power-aware technology mapping for LUT-based FPGAs. - Jason Helge Anderson; Farid N. Najm (FPT, 2002)

Switching activity analysis and pre-layout activity prediction for FPGAs. - Jason Helge Anderson; Farid N. Najm (SLIP, 2003)

Interconnect capacitance estimation for FPGAs. - Jason Helge Anderson; Farid N. Najm (ASP-DAC, 2004)

A novel low-power FPGA routing switch. - Jason Helge Anderson; Farid N. Najm (CICC, 2004)

Active leakage power optimization for FPGAs. - Jason Helge Anderson; Farid N. Najm; Tim Tuan (FPGA, 2004)

Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. - Jason Helge Anderson; Sudip Nag; Kamal Chaudhary; Sandor Kalman; Chari Madabhushi; Paul Cheng (FPL, 2004)

Low-power programmable routing circuitry for FPGAs. - Jason Helge Anderson; Farid N. Najm (ICCAD, 2004)

Power estimation techniques for FPGAs. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Active leakage power optimization for FPGAs. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

CAD Techniques for Power Optimization in Virtex-5 FPGAs. - Subodh Gupta; Jason Helge Anderson; Linda Farragher; Qiang Wang (CICC, 2007)

Architecture-specific packing for virtex-5 FPGAs. - Taneem Ahmed; Paul D. Kundarewich; Jason Helge Anderson; Brad L. Taylor; Rajat Aggarwal (FPGA, 2008)

Emerging application domains: research challenges and opportunities for FPGAs. - Jason Helge Anderson (FPGA, 2009)

Clock power reduction for virtex-5 FPGAs. - Qiang Wang; Subodh Gupta; Jason Helge Anderson (FPGA, 2009)

Improving logic density through synthesis-inspired architecture. - Jason Helge Anderson; Qiang Wang (FPL, 2009)

Clock gating architectures for FPGA power reduction. - Safeen Huda; Muntasir Mallick; Jason Helge Anderson (FPL, 2009)

Packing Techniques for Virtex-5 FPGAs. - Taneem Ahmed; Paul D. Kundarewich; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2009)

Low-Power Programmable FPGA Routing Circuitry. - Jason Helge Anderson; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A PUF design for secure FPGA-based embedded systems. - Jason Helge Anderson (ASP-DAC, 2010)

FPGA power reduction by guarded evaluation. - Jason Helge Anderson; Chirag Ravishankar (FPGA, 2010)

Parallelizing FPGA placement using Transactional Memory. - Steven Birk; J. Gregory Steffan; Jason Helge Anderson (FPT, 2010)

Deterministic multi-core parallel routing for FPGAs. - Marcel Gort; Jason Helge Anderson (FPT, 2010)

Low-cost hardware profiling of run-time and energy in FPGA embedded processors. - Mark Aldham; Jason Helge Anderson; Stephen Brown 003; Andrew Canis (ASAP, 2011)

Area-efficient FPGA logic elements: Architecture and synthesis. - Jason Helge Anderson; Qiang Wang (ASP-DAC, 2011)

An integer programming placement approach to FPGA clock power reduction. - Alireza Rakhshanfar; Jason Helge Anderson (ASP-DAC, 2011)

LegUp: high-level synthesis for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2011)

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. - Jason Luu; Jason Helge Anderson; Jonathan Rose (FPGA, 2011)

Reducing FPGA Router Run-Time through Algorithm and Architecture. - Marcel Gort; Jason Helge Anderson (FPL, 2011)

Latch-Based Performance Optimization for FPGAs. - Bill Teng; Jason Helge Anderson (FPL, 2011)

FPGA glitch power analysis and reduction. - Warren Wai-Kit Shum; Jason Helge Anderson (ISLPED, 2011)

Leveraging reconfigurability to raise productivity in FPGA functional debug. - Zissis Poulos; Yu-Shen Yang; Jason Helge Anderson; Andreas G. Veneris; Bao Le (DATE, 2012)

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. - Jongsok Choi; Kevin Nam; Andrew Canis; Jason Helge Anderson; Stephen Brown 003; Tomasz S. Czajkowski (FCCM, 2012)

Impact of FPGA architecture on resource sharing in high-level synthesis. - Stefan Hadjis; Andrew Canis; Jason Helge Anderson; Jongsok Choi; Kevin Nam; Stephen Brown 003; Tomasz S. Czajkowski (FPGA, 2012)

The VTR project: architecture and CAD for FPGAs from verilog to routing. - Jonathan Rose; Jason Luu; Chi Wai Yu; Opal Densmore; Jeffrey Goeders; Andrew Somerville; Kenneth B. Kent; Peter Jamieson; Jason Helge Anderson (FPGA, 2012)

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. - Warren Wai-Kit Shum; Jason Helge Anderson (FPGA, 2012)

Analytical placement for heterogeneous FPGAs. - Marcel Gort; Jason Helge Anderson (FPL, 2012)

FPGA power reduction by guarded evaluation considering physical information. - Chirag Ravishankar; Andrew A. Kennings; Jason Helge Anderson (VLSI-SoC, 2012)

Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. - Marcel Gort; Jason Helge Anderson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. - Chirag Ravishankar; Jason Helge Anderson; Andrew A. Kennings (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Raising FPGA Logic Density Through Synthesis-Inspired Architecture. - Jason Helge Anderson; Qiang Wang; Chirag Ravishankar (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Range and bitmask analysis for hardware optimization in high-level synthesis. - Marcel Gort; Jason Helge Anderson (ASP-DAC, 2013)

From software to accelerators with LegUp high-level synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Ruolong Lian; Qijing Huang 001; Nazanin Calagar; Marcel Gort; Jia Jun Qin; Mark Aldham; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (CASES, 2013)

Multi-pumping for resource reduction in FPGA high-level synthesis. - Andrew Canis; Jason Helge Anderson; Stephen Dean Brown (DATE, 2013)

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Stephen Brown 003; Jason Helge Anderson (FCCM, 2013)

High-level synthesis with LegUp: a crash course for users and researchers. - Jason Helge Anderson; Stephen Dean Brown; Andrew Canis; Jongsok Choi (FPGA, 2013)

Charge recycling for power reduction in FPGA interconnect. - Safeen Huda; Jason Helge Anderson; Hirotaka Tamura (FPL, 2013)

From C to Blokus Duo with LegUp high-level synthesis. - Jiu Cheng Cai; Ruolong Lian; Mengyao Wang; Andrew Canis; Jongsok Choi; Blair Fort; Eric Hart; Emily Miao; Yanyan Zhang; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (FPT, 2013)

A case for hardened multiplexers in FPGAs. - S. Alexander Chin; Jason Helge Anderson (FPT, 2013)

From software threads to parallel hardware in high-level synthesis for FPGAs. - Jongsok Choi; Stephen Brown 003; Jason Helge Anderson (FPT, 2013)

Bitwidth-optimized hardware accelerators with software fallback. - Ana Klimovic; Jason Helge Anderson (FPT, 2013)

DistCL: A Framework for the Distributed Execution of OpenCL Kernels. - Tahir Diop; Steven Gurfinkel; Jason Helge Anderson; Natalie D. Enright Jerger (MASCOTS, 2013)

Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance. - Edgar Mora-Sanchez; Jason Helge Anderson (ReConFig, 2013)

Latch-Based Performance Optimization for Field-Programmable Gate Arrays. - Bill Teng; Jason Helge Anderson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. - Andrew Canis; Jongsok Choi; Mark Aldham; Victor Zhang; Ahmed Kammoona; Tomasz S. Czajkowski; Stephen Dean Brown; Jason Helge Anderson (ACM Trans. Embed. Comput. Syst., 2013)

Combined Architecture/Algorithm Approach to Fast FPGA Routing. - Marcel Gort; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power Modeling for Heterogeneous Processors. - Tahir Diop; Natalie D. Enright Jerger; Jason Helge Anderson (GPGPU@ASPLOS, 2014)

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. - Blair Fort; Andrew Canis; Jongsok Choi; Nazanin Calagar; Ruolong Lian; Stefan Hadjis; Yu Ting Chen; Mathew Hall; Bain Syrowik; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (EUC, 2014)

On Hard Adders and Carry Chains in FPGAs. - Jason Luu; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (FCCM, 2014)

Optimizing effective interconnect capacitance for FPGA power reduction. - Safeen Huda; Jason Helge Anderson; Hirotaka Tamura (FPGA, 2014)

Towards interconnect-adaptive packing for FPGAs. - Jason Luu; Jonathan Rose; Jason Helge Anderson (FPGA, 2014)

Source-level debugging for FPGA high-level synthesis. - Nazanin Calagar; Stephen Dean Brown; Jason Helge Anderson (FPL, 2014)

Modulo SDC scheduling with recurrence minimization in high-level synthesis. - Andrew Canis; Stephen Dean Brown; Jason Helge Anderson (FPL, 2014)

Design re-use for compile time reduction in FPGA high-level synthesis flows. - Marcel Gort; Jason Helge Anderson (FPT, 2014)

Approaching overhead-free execution on FPGA soft-processors. - Charles Eric LaForest; Jason Helge Anderson; J. Gregory Steffan (FPT, 2014)

Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12). - Jason Helge Anderson; Kiyoung Choi (ACM Trans. Reconfigurable Technol. Syst., 2014)

VTR 7.0: Next Generation Architecture and CAD System for FPGAs. - Jason Luu; Jeffrey Goeders; Michael Wainberg; Andrew Somerville; Thien Yu; Konstantin Nasartschuk; Miad Nasr; Sen Wang; Tim Liu; Nooruddin Ahmed; Kenneth B. Kent; Jason Helge Anderson; et al. (ACM Trans. Reconfigurable Technol. Syst., 2014)

Profiling-driven multi-cycling in FPGA high-level synthesis. - Stefan Hadjis; Andrew Canis; Ryoya Sobue; Yuko Hara-Azumi; Hiroyuki Tomiyama; Jason Helge Anderson (DATE, 2015)

Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. - Tanvir Ahmed 004; Noriaki Sakamoto; Jason Helge Anderson; Yuko Hara-Azumi (EUC, 2015)

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. - Jin Hee Kim; Jason Helge Anderson (FPL, 2015)

Significant papers from the first 25 years of the FPL conference. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (FPL, 2015)

Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. - Jongsok Choi; Stephen Brown 003; Jason Helge Anderson (FPT, 2015)

The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2015)

LegUp High-Level Synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Bain Syrowik; Ruolong Lian; Yu Ting Chen; Hsuan Hsiao; Jeffrey B. Goeders; Stephen Brown 003; Jason Helge Anderson (FPGAs for Software Programmers, 2016)

A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. - Jongsok Choi; Ruolong Lian; Stephen Brown 003; Jason Helge Anderson (ASAP, 2016)

Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. - Jason Helge Anderson; Yuko Hara-Azumi; Shigeru Yamashita (DATE, 2016)

Towards PVT-Tolerant Glitch-Free Operation in FPGAs. - Safeen Huda; Jason Helge Anderson (FPGA, 2016)

Preface. - Paolo Ienne; Walid A. Najjar; Jason Helge Anderson; Philip Brisk; Walter Stechele (FPL, 2016)

High-level synthesis - the right side of history. - Jason Helge Anderson (FPT, 2016)

Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. - Safeen Huda; Jason Helge Anderson (ISPD, 2016)

A Survey and Evaluation of FPGA High-Level Synthesis Tools. - Razvan Nane; Vlad Mihai Sima; Christian Pilato; Jongsok Choi; Blair Fort; Andrew Canis; Yu Ting Chen; Hsuan Hsiao; Stephen Brown 003; Fabrizio Ferrandi; Jason Helge Anderson; Koen Bertels (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Hybrid LUT/Multiplexer FPGA Logic Architectures. - S. Alexander Chin; Jason Luu; Safeen Huda; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2016)

CGRA-ME: A unified framework for CGRA modelling and exploration. - S. Alexander Chin; Noriaki Sakamoto; Allan Rui; Jim Zhao; Jin Hee Kim; Yuko Hara-Azumi; Jason Helge Anderson (ASAP, 2017)

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. - Yu Ting Chen; Jason Helge Anderson (FPL, 2017)

FPGA-based CNN inference accelerator synthesized from multi-threaded C software. - Jin Hee Kim; Brett Grady; Ruolong Lian; John Brothers; Jason Helge Anderson (SoCC, 2017)

Subleq⊝: An Area-Efficient Two-Instruction-Set Computer. - Noriaki Sakamoto; Tanvir Ahmed 004; Jason Helge Anderson; Yuko Hara-Azumi (IEEE Embed. Syst. Lett., 2017)

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. - Jin Hee Kim; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2017)

Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays. - Charles Eric LaForest; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2017)

The First 25 Years of the FPL Conference: Significant Papers. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (ACM Trans. Reconfigurable Technol. Syst., 2017)

From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. - Jongsok Choi; Stephen Dean Brown; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. - Safeen Huda; Jason Helge Anderson (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An architecture-agnostic integer linear programming approach to CGRA mapping. - S. Alexander Chin; Jason Helge Anderson (DAC, 2018)

High-level synthesis of software-customizable floating-point cores. - Samridhi Bansal; Hsuan Hsiao; Tomasz S. Czajkowski; Jason Helge Anderson (DATE, 2018)

Sensei: An area-reduction advisor for FPGA high-level synthesis. - Hsuan Hsiao; Jason Helge Anderson (DATE, 2018)

High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. - Omar Ragheb; Jason Helge Anderson (FCCM, 2018)

Software-Specified FPGA Accelerators for Elementary Functions. - Jing Chen; Xue Liu; Jason Helge Anderson (FPT, 2018)

Synthesizable Heterogeneous FPGA Fabrics. - Brett Grady; Jason Helge Anderson (FPT, 2018)

FPGA Architecture Enhancements for Efficient BNN Implementation. - Jin Hee Kim; Jongeun Lee; Jason Helge Anderson (FPT, 2018)

Compact Area and Performance Modelling for CGRA Architecture Evaluation. - Kuang Ping Niu; Jason Helge Anderson (FPT, 2018)

Accelerating Memcached on AWS Cloud FPGAs. - Jongsok Choi; Ruolong Lian; Zhi Li; Andrew Canis; Jason Helge Anderson (HEART, 2018)

Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. - S. Alexander Chin; Kuang Ping Niu; Matthew J. P. Walker; Shizhang Yin; Alexander Mertens; Jongeun Lee; Jason Helge Anderson (ISPD, 2018)

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. - Hyeon Uk Sim; Jason Helge Anderson; Jongeun Lee (ASP-DAC, 2019)

Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis. - Hsuan Hsiao; Jason Helge Anderson (DAC, 2019)

Impact of FPGA Architecture on Area and Performance of CGRA Overlays. - Ian Taras; Jason Helge Anderson (FCCM, 2019)

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. - Matthew J. P. Walker; Jason Helge Anderson (FCCM, 2019)

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. - Jianyi Cheng; Shane T. Fleming; Yu Ting Chen; Jason Helge Anderson; George A. Constantinides (FPGA, 2019)

A Dynamic Memory Allocation Library for High-Level Synthesis. - Nicholas V. Giamblanco; Jason Helge Anderson (FPL, 2019)

Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs. - Brett Grady; Jason Helge Anderson (HEART, 2019)

High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. - Yu Ting Chen; Jin Hee Kim; Kexin Li; Graham Hoyes; Jason Helge Anderson (FPT, 2019)

ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis. - Nicholas V. Giamblanco; Jason Helge Anderson (FPT, 2019)

Optimizing FPGA Logic Block Architectures for Arithmetic. - Kevin E. Murray; Jason Luu; Matthew J. P. Walker; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). - Jason Helge Anderson; Rami Beidas; Vimal Chacko; Hsuan Hsiao; Xiaoyi Ling; Omar Ragheb; Xinyuan Wang 003; Tianyi Yu (ASAP, 2021)

Power, Performance and Area Consequences of Multi-Context Support in CGRAs. - Vimal Chacko; Jason Helge Anderson (ASAP, 2021)

Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays. - Xinyuan Wang 003; Tianyi Yu; Hsuan Hsiao; Jason Helge Anderson (ASAP, 2021)

Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. - Hsuan Hsiao; Joshua San Miguel; Yuko Hara-Azumi; Jason Helge Anderson (ASP-DAC, 2021)

High-Level Synthesis of Transactional Memory. - Omar Ragheb; Jason Helge Anderson (ASP-DAC, 2021)

An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. - Xiaoyi Ling; Takahiro Notsu; Jason Helge Anderson (DSD, 2021)

Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. - Jin Hee Kim; Jason Helge Anderson (FPL, 2021)

Profiling-Based Control-Flow Reduction in High-Level Synthesis. - Austin Liolli; Omar Ragheb; Jason Helge Anderson (FPT, 2021)

Dynamic Power Analysis of Standard-Cell FPGA Fabrics. - Bo Bao; Jason Anderson 001 (SoCC, 2021)

CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. - Rami Beidas; Jason Helge Anderson (ASP-DAC, 2022)

Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. - Hsuan Hsiao; Joshua San Miguel; Jason Helge Anderson (ASP-DAC, 2022)

Modeling and Exploration of Elastic CGRAs. - Omar Ragheb; Tianyi Yu; David Ma; Jason Helge Anderson (FPL, 2022)

The First International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC). - Artur Podobas; Kentaro Sano; Jason Anderson 001 (IPDPS Workshops, 2022)

Elastic Multi-Context CGRAs. - Omar Ragheb; Tianyi Yu; Rami Beidas; Jason Helge Anderson (IPDPS Workshops, 2022)

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. - Jianyi Cheng; Shane T. Fleming; Yu Ting Chen; Jason Helge Anderson; John Wickerson; George A. Constantinides (IEEE Trans. Computers, 2022)

Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. - Guanglei Zhou; Jason Helge Anderson (ASP-DAC, 2023)

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. - Guanglei Zhou; Mirjana Stojilovic; Jason Helge Anderson (FPL, 2023)

Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC. - Jason Anderson 001; Boma A. Adhi; Carlos Cortes; Emanuele Del Sozzo; Omar Ragheb; Kentaro Sano (HEART, 2023)

Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility. - Omar Ragheb; Rami Beidas; Jason Helge Anderson (IPDPS Workshops, 2023)

Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization. - Salim Khemira; Xinyuan Wang; Anh Nguyen; Yutaka Tamiya; Makoto Taiji; Takahide Yoshikawa; Jason Helge Anderson (ASAP, 2024)

MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs. - Tianyi Yu; Omar Ragheb; Stephen Wicklund; Jason Helge Anderson (ASAP, 2024)

CLUMAP: Clustered Mapper for CGRAs with Predication. - Omar Ragheb; Jason Helge Anderson (DAC, 2024)

Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams. - Rami Beidas; Jason Helge Anderson (FCCM, 2024)

CAD Techniques for NoC-Connected Multi-CGRA Systems. - Haoran Wei; Omkar Bhilare; Hamas Waqar; Jason Helge Anderson (HEART, 2024)

CGRA-ME 2.0: A Research Framework for Next-Generation CGRA Architectures and CAD. - Omar Ragheb; Stephen Wicklund; Matthew Walker; Rami Beidas; Adham Ragab; Tianyi Yu; Jason Helge Anderson (IPDPS (Workshops), 2024)

Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA. - Emanuele Del Sozzo; Xinyuan Wang 003; Boma A. Adhi; Carlos Cortes; Jason Anderson 001; Kentaro Sano (IPDPS, 2024)

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. - Louis Coulon; Lucas Ramirez; Jason Helge Anderson; Mirjana Stojilovic; Paolo Ienne (FPGA, 2025)

Impact of Reconvergent DFG Paths and Buffer Depth on Elastic CGRA Throughput. - Yasuto Aihara; Boma Anantasatya Adhi; Kota Aiyoshi; Chenlin Shi; Jason Anderson 001; Tomohiro Ueno; Kentaro Sano; Takaaki Miyajima (HEART, 2025)

Systolic Array-Based Matrix Multiplication and Reduction on Elastic CGRAs. - Aditya Srichandan; Omar Ragheb; Jason Helge Anderson (HEART, 2025)

RAAP-CGRA: Placement for CGRAs with Restricted Routing Architectures. - Anh Nguyen; Sebastian Czyrny; Takahide Yoshikawa; Jason Helge Anderson (IPDPS (Workshops), 2025)