A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

Testing High-Speed IO Links Using On-Die Circuitry. - Priya Iyer; Shailendra Jain; Bryan Casper; Jason Howard (VLSI Design, 2006)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Priya Iyer; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Sriram Venkataraman; et al. (ISSCC, 2007)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Vasantha Erraguntla; Clark Roberts; et al. (IEEE J. Solid State Circuits, 2008)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

The 48-core SCC Processor: the Programmer's View. - Timothy G. Mattson; Michael Riepen; Thomas Lehnig; Paul Brett; Werner Haas 002; Patrick Kennedy; Jason Howard; Sriram R. Vangal; Nitin Borkar; Gregory Ruhl; Saurabh Dighe (SC, 2010)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

Resiliency for many-core system on a chip. - Tanay Karnik; James W. Tschanz; Nitin Borkar; Jason Howard; Sriram R. Vangal; Vivek De; Shekhar Borkar (ASP-DAC, 2014)

PIUMA: Programmable Integrated Unified Memory Architecture. - Sriram Aananthakrishnan; Nesreen K. Ahmed; Vincent Cavé; Marcelo Cintra; Yigit Demir; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Ivan Ganev; Wim Heirman; Hans-Christian Hoppe; Jason Howard; et al. (CoRR, 2020)

The First Direct Mesh-to-Mesh Photonic Fabric. - Jason Howard (HCS, 2023)

The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. - Sriram Aananthakrishnan; Shamsul Abedin; Vincent Cavé; Fabio Checconi; Kristof Du Bois; Stijn Eyerman; Joshua B. Fryman; Wim Heirman; Jason Howard; Ibrahim Hur; Samkit Jain; Marek M. Landowski; et al. (IEEE Micro, 2023)

Cross-Domain Solutions (CDS): A Comprehensive Survey. - Vignesh Sundaravarathan; Husain Alqalaf; Asif Siddiqui; Kiju Kim; Sanghee Lee; Martin Reisslein; Akhilesh S. Thyagaturu; Nick Ross; Jason Howard; Sanjaya Tayal (IEEE Access, 2024)

The First Direct Mesh-to-Mesh Photonic Fabric. - Jason Howard; Joshua B. Fryman; Shamsul Abedin (IEEE Micro, 2024)

Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation. - Vignesh Sundaravarathan; Martin Reisslein; Akhilesh S. Thyagaturu; Nick Ross; Gurpreet Singh Kalsi; Jason Howard; Jan Kaisrlik; Bartosz Matwiejczyk; Marek M. Landowski; Piotr Dorozynski; Harvey Vrsalovic; Sanjaya Tayal (IEEE Access, 2025)