An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (CICC, 2007)

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISSCC, 2007)

A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (CICC, 2008)

Circuit techniques for ultra-low power subthreshold SRAMs. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISCAS, 2008)

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (IEEE J. Solid State Circuits, 2008)

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (IEEE J. Solid State Circuits, 2009)