Verifying information flow properties of firmware using symbolic execution. - Pramod Subramanyan; Sharad Malik; Hareesh Khattri; Abhranil Maiti; Jason M. Fung (DATE, 2016)

Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities. - Swarup Bhunia; An Chen; Ozgur Sinanoglu; Jason M. Fung (IEEE Trans. Emerg. Top. Comput., 2017)

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. - Bo-Yuan Huang 001; Sayak Ray; Aarti Gupta; Jason M. Fung; Sharad Malik (DAC, 2018)

When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs. - Ghada Dessouky; David Gens; Patrick Haney; Garrett Persyn; Arun K. Kanuparthi; Hareesh Khattri; Jason M. Fung; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (CoRR, 2018)

Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs. - Sayak Ray; Nishant Ghosh; Ramya Jayaram Masti; Arun K. Kanuparthi; Jason M. Fung (DAC, 2019)

HardFails: Insights into Software-Exploitable Hardware Bugs. - Ghada Dessouky; David Gens; Patrick Haney; Garrett Persyn; Arun K. Kanuparthi; Hareesh Khattri; Jason M. Fung; Ahmad-Reza Sadeghi; Jeyavijayan Rajendran (USENIX Security Symposium, 2019)

Methodology of Assessing Information Leakage through Software-Accessible Telemetries. - Chen Liu 013; Monodeep Kar; Xueyang Wang; Nikhil Chawla; Neer Roggel; Bilgiday Yuce; Jason M. Fung (HOST, 2021)

Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions. - Naghmeh Karimi; Kanad Basu; Chip-Hong Chang; Jason M. Fung (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security. - Wenye Liu; Chip-Hong Chang; Xueyang Wang; Chen Liu 013; Jason M. Fung; Mohammad Ebrahimabadi; Naghmeh Karimi; Xingyu Meng; Kanad Basu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip. - Benjamin Tan 001; Rana Elnaggar; Jason M. Fung; Ramesh Karri; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Automating hardware security property generation: invited. - Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Sayak Ray; Jason M. Fung; Cynthia Sturton (DAC, 2022)

Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design. - Baleegh Ahmad; Wei-Kai Liu; Luca Collini; Hammond Pearce; Jason M. Fung; Jonathan Valamehr; Mohammad Bidmeshki; Piotr Sapiecha; Steve Brown; Krishnendu Chakrabarty; Ramesh Karri; Benjamin Tan 001 (ICCAD, 2022)

Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK. - Anupam Golder; Debayan Das; Santosh Ghosh; Avinash Varna 001; Majid Sabbagh; Sayak Ray; Rana Elnaggar; Joseph Friel; Daniel Dinu; Jason M. Fung (DAC, 2023)

Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. - Tobias Jauch; Alex Wezel; Mohammad Rahmani Fadiheh; Philipp Schmitz; Sayak Ray; Jason M. Fung; Christopher W. Fletcher; Dominik Stoffel; Wolfgang Kunz (ICCAD, 2023)

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. - Mohammad Rahmani Fadiheh; Alex Wezel; Johannes Müller 006; Jörg Bormann; Sayak Ray; Jason M. Fung; Subhasish Mitra; Dominik Stoffel; Wolfgang Kunz (IEEE Trans. Computers, 2023)

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks. - Wei-Kai Liu; Benjamin Tan 001; Jason M. Fung; Ramesh Karri; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Theoretical Patchability Quantification for IP-Level Hardware Patching Designs. - Wei-Kai Liu; Benjamin Tan 001; Jason M. Fung; Krishnendu Chakrabarty (ASPDAC, 2024)

Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. - Debayan Das; Majid Sabbagh; Rana Elnaggar; Guang Chen; Sayak Ray; Jason M. Fung (VLSID, 2024)

RAG-Based Fuzzing of Cross-Architecture Compilers. - Rana Elnaggar; Brian Delgado; Jason M. Fung (CoRR, 2025)