Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. - Greg Stitt; Brian Grattan; Jason R. Villarreal; Frank Vahid (FCCM, 2002)

Improving Software Performance with Configurable Logic. - Jason R. Villarreal; Dinesh C. Suresh; Greg Stitt; Frank Vahid; Walid A. Najjar (Des. Autom. Embed. Syst., 2002)

Profiling tools for hardware/software partitioning of embedded applications. - Dinesh C. Suresh; Walid A. Najjar; Frank Vahid; Jason R. Villarreal; Greg Stitt (LCTES, 2003)

Compiled hardware acceleration of Molecular Dynamics code. - Jason R. Villarreal; Walid A. Najjar (FPL, 2008)

Recursion flattening. - Greg Stitt; Jason R. Villarreal (ACM Great Lakes Symposium on VLSI, 2008)

Reconfigurable Computing in the New Age of Parallelism. - Walid A. Najjar; Jason R. Villarreal (SAMOS, 2009)

Designing Modular Hardware Accelerators in C with ROCCC 2.0. - Jason R. Villarreal; Adrian Park 002; Walid A. Najjar; Robert J. Halstead (FCCM, 2010)

Impact of high-level transformations within the ROCCC framework. - Betul Buyukkurt; John Cortes; Jason R. Villarreal; Walid A. Najjar (ACM Trans. Archit. Code Optim., 2010)

Exploring irregular memory accesses on FPGAs. - Robert J. Halstead; Jason R. Villarreal; Walid A. Najjar (IA3@SC, 2011)

Multithreaded FPGA acceleration of DNA sequence mapping. - Edward Fernandez; Walid A. Najjar; Stefano Lonardi; Jason R. Villarreal (HPEC, 2012)

FPGA code accelerators - the compiler perspective. - Walid A. Najjar; Jason R. Villarreal (DAC, 2013)

Compiling irregular applications for reconfigurable systems. - Robert J. Halstead; Jason R. Villarreal; Walid A. Najjar (Int. J. High Perform. Comput. Netw., 2014)

FHAST: FPGA-Based Acceleration of Bowtie in Hardware. - Edward B. Fernandez; Jason R. Villarreal; Stefano Lonardi; Walid A. Najjar (IEEE ACM Trans. Comput. Biol. Bioinform., 2015)

ROCCC 2.0. - Walid A. Najjar; Jason R. Villarreal; Robert J. Halstead (FPGAs for Software Programmers, 2016)