An Integrated Framework to Support Distributed CAD over the Internet. - Amar Gupta; Sanjeev Vadhavkar; Feniosky Peña-Mora; Jason Yeung (WETICE, 2001)

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. - Socrates D. Vamvakos; Bendik Kleveland; Dipak K. Sikdar; B. K. Ahuja; Haidang Lin; Jayaprakash Balachandran; Wignes Balakrishnan; Aldo Bottelli; Jawji Chen; Xiaole Chen; Jae Choi; Jeong Choi; et al. (ESSCIRC, 2012)

A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications. - Socrates D. Vamvakos; Claude R. Gauthier; Chethan Rao; Karthisha Ramoshan Canagasaby; Prashant Choudhary; Sanjay Dabral; Shaishav Desai; Mahmudul Hassan; Kuo-Chiang Hsieh; Bendik Kleveland; Gurupada Mandal; Richard Rouse; et al. (MWSCAS, 2012)

A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. - Socrates D. Vamvakos; Charles Boecker; Eric Groen; Alvin Wang; Shaishav Desai; Scott Irwin; Vithal Rao; Aldo Bottelli; Jawji Chen; Xiaole Chen; Prashant Choudhary; Kuo-Chiang Hsieh; et al. (CICC, 2014)

ViReMaShiny: an interactive application for analysis of viral recombination data. - Jason Yeung; Andrew L. Routh (Bioinform., 2022)