A multiword based high speed ECC scheme for low-voltage embedded SRAMS. - Shah M. Jahinuzzaman; Tahseen Shakir; Sumanjit Lubana; Jaspal Singh Shah; Manoj Sachdev (ESSCIRC, 2008)

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. - Shah M. Jahinuzzaman; Jaspal Singh Shah; David J. Rennie; Manoj Sachdev (IEEE J. Solid State Circuits, 2009)

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. - Jaspal Singh Shah; David Nairn; Manoj Sachdev (VLSI-SoC, 2012)

An Energy-Efficient Offset-Cancelling Sense Amplifier. - Jaspal Singh Shah; David Nairn; Manoj Sachdev (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Radiation hardened pulsed-latches in 65-nm CMOS. - Jaspal Singh Shah; Manoj Sachdev (CCECE, 2016)