Verification of Power-based Side-channel Leakage through Simulation. - Yuan Yao; Patrick Schaumont; Jasper Van Woudenberg; Cees-Bart Breunesse; Edgar Mateos Santillan; Steve Stecyk (MWSCAS, 2020)

Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection. - Pantea Kiaei; Cees-Bart Breunesse; Mohsen Ahmadi; Patrick Schaumont; Jasper Van Woudenberg (DAC, 2021)

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (CoRR, 2022)

Invited: Pre-silicon Side Channel and Fault Analysis. - Jasper Van Woudenberg; Peter Grossmann; Avinash Varna 001; Joseph Friel; Daniel Dinu; Ronnie Lindsay; Steve J. Brown (DAC, 2023)

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. - Sohrab Aftabjahani; Mark Tehranipoor; Farimah Farahmandi; Bulbul Ahmed; Ryan Kastner; Francesco Restuccia 002; Andres Meza 001; Kaki Ryan; Nicole Fern; Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; et al. (VTS, 2023)

Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models. - Jasper Van Woudenberg; Rajesh Velegalati; Cees-Bart Breunesse; Dennis Vermoen Riscure (FDTC, 2024)

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2024)