Data trace cache: an application specific cache architecture. - Subramanian Ramaswamy; Jaswanth Sreeram; Sudhakar Yalamanchili; Krishna V. Palem (SIGARCH Comput. Archit. News, 2006)

RSTM : A Relaxed Consistency Software Transactional Memory for Multicores. - Jaswanth Sreeram; Romain Cledat; Tushar Kumar; Santosh Pande (PACT, 2007)

A profile-driven statistical analysis framework for the design optimization of soft real-time applications. - Tushar Kumar; Jaswanth Sreeram; Romain Cledat; Santosh Pande (ESEC/SIGSOFT FSE, 2007)

Statistically Analyzing Execution Variance for Soft Real-Time Applications. - Tushar Kumar; Romain Cledat; Jaswanth Sreeram; Santosh Pande (LCPC, 2008)

Exploiting approximate value locality for data synchronization on multi-core processors. - Jaswanth Sreeram; Santosh Pande (IISWC, 2010)

Parallelizing a Real-Time Physics Engine Using Transactional Memory. - Jaswanth Sreeram; Santosh Pande (Euro-Par (2), 2011)

Enriching 3-D Video Games on Multicores. - Romain Cledat; Tushar Kumar; Jaswanth Sreeram; Santosh Pande (IPDPS, 2011)

Optimistic semantic synchronization. - Jaswanth Sreeram (2011)

Parallel Programming for the Web. - Stephan Herhut; Richard L. Hudson; Tatiana Shpeisman; Jaswanth Sreeram (HotPar, 2012)

Hybrid Transactions: Lock Allocation and Assignment for Irrevocability. - Jaswanth Sreeram; Santosh Pande (IPDPS, 2012)

Safe compiler-driven transaction checkpointing and recovery. - Jaswanth Sreeram; Santosh Pande (OOPSLA, 2012)

River trail: a path to parallelism in JavaScript. - Stephan Herhut; Richard L. Hudson; Tatiana Shpeisman; Jaswanth Sreeram (OOPSLA, 2013)

Parallel JavaScript: bringing the compute power of multi-core CPUs and GPUs to the world of web graphics. - Stephan Herhut; Richard L. Hudson; Tatiana Shpeisman; Jaswanth Sreeram (SIGGRAPH Talks, 2013)

Are Web Applications Ready for Parallelism? - Cosmin Radoi; Stephan Herhut; Jaswanth Sreeram; Danny Dig (HICSS, 2017)