High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. - Prabhu Rajamani; Jatan P. Shah; Vadhiraj Sankaranarayanan; Rama Sangireddy (IPCCC, 2006)

Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. - Jatan P. Shah; Rama Sangireddy (ISCAS, 2007)

Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. - Rama Sangireddy; Jatan P. Shah (IEEE Trans. Parallel Distributed Syst., 2008)