Sub-clock power-gating technique for minimising leakage power during active mode. - Jatin N. Mistry; Bashir M. Al-Hashimi; David Flynn; Stephen Hill (DATE, 2011)

dRail: A Novel Physical Layout Methodology for Power Gated Circuits. - Jatin N. Mistry; John Biggs; James Myers; Bashir M. Al-Hashimi; David Flynn (PATMOS, 2012)

Leakage power minimisation techniques for embedded processors. - Jatin N. Mistry (2013)

Active Mode Subclock Power Gating. - Jatin N. Mistry; James Myers; Bashir M. Al-Hashimi; David Flynn; John Biggs; Geoff V. Merrett (IEEE Trans. Very Large Scale Integr. Syst., 2014)